US4164436A
Expired / Lapsed
US
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Process for preparation of semiconductor devices utilizing a two-step polycrystalline deposition technique to form a diffusion source
Assignee: Hitachi Ltd
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Filing: 1978-07-18
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Granted: 1979-08-14
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Expires: 1998-07-18
Abstract
Abstract A semiconductor substrate having a single crystal semiconductor layer of one conductivity type exposed to the surface thereof is maintained at a temperature lower than the temperature at which the semiconductors is precipitated from the gas phase. In this state, a gas of a starting material of a semiconductor, a gas containing impurities capable of forming a semiconductor of the other conductivity type and a carrier gas therefore are fed onto the semiconductor substrate. Then, the semiconductor substrate is heated to form an amorphous or polycrystalline semiconductor layer of the other conductivity type on the semiconductor substrate. Simultaneously, the impurities of the other conductivity type are diffused from the amorphous or polycrystal semiconductor layer into the substrate which has a single crystal semiconductor layer of one conductivity type, to form a single crystal semiconductor layer having a p-n junction just below the amorphous or polycrystal semiconductor layer between the amorphous or polycrystalline semiconductor layer and the single crystal semiconductor layer of one conductivity type. In a p-n junction to be formed according to this process, the distribution of the concentration of impurities can be controlled precisely, and the step-like distribution of the concentration of impurities can be attained very well.
Inventors
- 👤 Mitsuru Ura
- 👤 Kenji Miyata
- 👤 Takaya Suzuki
- 👤 Takuzo Ogawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:03
CPC Classifications
H; H10; H10D; H10D8/00; H10D8/20; H10D8/25; H10D62/00; H10D62/10; H10D62/13; H10D62/141; H10D62/142; H10D62/40; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/32; H10P14/3202; H10P14/3204; H10P14/3211; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P14/3438; H10P14/3441; H10P14/3442; H10P14/3444; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S148/00; Y10S148/122; Y10S438/00; Y10S438/983
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
193 words
A process for the preparation of semiconductor devices, which comprises the steps of: (a) maintaining a semiconductor substrate having a semiconductor single crystal region of one conductivity type exposed on one main surface thereof, at a temperature lower than the temperature causing substantial precipitation of a semiconductor from the gas phase, (b) initiating supply of a gaseous mixture comprising a gas of a starting substance of a semiconductor, a gas of impurities capable of providing a semiconductor of the other conductivity type and a carrier gas therefor to said main surface of the semiconductor substrate, (c) heating said semiconductor substrate to grow from the gas phase an amorphous or polycrystalline semiconductor layer of the other conductor type on said one main surface of the semiconductor substrate and diffuse the impurities deciding the conductor type of the amorphous or polycrystalline semiconductor layer of the other conductivity type, into said semiconductor single crystal region of one conductivity type, whereby a semiconductor single crystal region of the other conductivity type is formed in said semiconductor single crystal region of one conductivity type, and (d) forming electrodes at predetermined positions including said amorphous or polycrystalline semiconductor layer.
Claim 2
Dependent Claim
193 words
A process for the preparation of semiconductor devices, which comprises the steps of: (a) maintaining a semiconductor substrate having a semiconductor single crystal region of one conductivity type exposed on one main surface thereof, at a temperature lower than the temperature causing substantial precipitation of a semiconductor from the gas phase, (b) initiating supply of a gaseous mixture comprising a gas of a starting substance of a semiconductor, a gas of impurities capable of providing a semiconductor of the other conductivity type and a carrier gas therefor to said main surface of the semiconductor substrate, (c) heating said semiconductor substrate to grow from the gas phase an amorphous or polycrystalline semiconductor layer of the other conductor type on said one main surface of the semiconductor substrate and diffuse the impurities deciding the conductor type of the amorphous or polycrystalline semiconductor layer of the other conductivity type, into said semiconductor single crystal region of one conductivity type, whereby a semiconductor single crystal region of the other conductivity type is formed in said semiconductor single crystal region of one conductivity type, and (d) forming electrodes at predetermined positions including said amorphous or polycrystalline semiconductor layer.
Claim 3
Dependent Claim
32 words
A process for the preparation of semiconductor devices according to claim 1 wherein at the step (a), the semiconductor substrate is maintained at a temperature ranging from room temperature to 500° C.
Claim 4
Dependent Claim
25 words
A process for the preparation of semiconductor devices according to claim 2 wherein at the step (a), the semiconductor substrate is maintained at room temperature.
Claim 5
Dependent Claim
58 words
A process for the preparation of semiconductor devices according to claim 1 wherein at the step (c), the growth of the amorphous or polycrystal semiconductor layer of the other conductivity type is conducted simultaneously with the formation of the semiconductor single crystal region of the other conductivity type in the semiconductor single crystal region of one conductivity type.
Claim 6
Dependent Claim
107 words
A process for the preparation of semiconductor devices according to claim 1 wherein the semiconductor substrate used at the step (a) has a pair of main surfaces and includes a first single crystal region of one conductivity type exposed to one main surface and a second single crystal region of the other conductivity type exposed to the other main surface and having an impurity concentration higher than that of the first single crystal region, and wherein at the step (d), a pair of electrodes are formed on the exposed surface of the amorphous or polycrystal semiconductor layer and the other main surface of the semiconductor substrate, respectively.
Claim 7
Dependent Claim
38 words
A process for the preparation of semiconductor devices according to claim 1 wherein the semiconductor substrate is composed of Si and the gas of the starting substance of the semiconductor is a gas of a compound containing Si.
Claim 8
Dependent Claim
145 words
A process for the preparation of semiconductor devices according to claim 6 wherein at the step (a), the semiconductor substrate is maintained at room temperature, at the step (b), a gas of SiHCl 3 and a gas of H 2 are used as the gas of the starting substance of the semiconductor and the carrier gas, respectively, and wherein at the step (c), the semiconductor substrate is heated at 900° to 950° C. to effect simultaneously the growth of a polycrystal Si layer of the other conductivity type and the formation of a single crystal Si region of the other conductivity type in the single crystal Si region of one conductivity type so that the quantity of the conductivity type-deciding impurities present in the single crystal Si region of the other conductivity type per unit area is 1×10 11 to 1×10 14 atoms/cm 2 .
Claim 9
Dependent Claim
142 words
A process for the preparation of semiconductor devices according to claim 1 wherein the semiconductor substrate used at the step (a) has a pair of main surfaces and includes a first single crystal region of one conductivity type exposed to one main surface, a second single crystal region of the other conductivity type contiguous to the first single crystal region and forming a p-n junction therewith and a third single crystal region of one conductor type contiguous to the second single crystal layer, exposed to the other main surface and forming a p-n junction with the second single crystal region, and wherein at the step (d), a pair of main electrodes are formed on the exposed main surface of the amorphous or polycrystal semiconductor layer and the exposed main surface of the first single crystal region on the other main surface, respectively.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-08-13 | 1983-02-12 | 1983-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-08-13 | 1987-02-12 | 1987-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-08-13 | 1991-02-12 | 1991-08-14 | $7700.00 | Window Closed / Lapsed |