US4164031A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory system
Assignee: Texas Instruments Inc
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Filing: 1976-11-26
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Granted: 1979-08-07
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Expires: 1996-11-26
Abstract
Abstract Disclosed is a memory system for storing digital data; the memory system of the type which may be implemented, for instance, in an electronic microprocessor or calculator system. The memory comprises an array of transistor memory cells arranged in columns and rows. Column conductors are provided for supplying digital information to each column of such cells and row conductors are provided for enabling each row of cells to store digital information being received on the column conductors. A commutator is provided for successively supplying enabling signals to the row conductors and another commutator is provided for successfully connecting the column conductors with an input/output bus in the memory system. The provision of the commutators with the array of memory cells causes the data, when stored as a word of data, to occupy a register arranged in essentially a diagonal pattern through the array.
Inventors
- 👤 Perry W. Lou
- 👤 Charles P. Grant, Jr., deceased
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 01:07
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405; G11C11/4063; G11C11/407; G11C11/408; G11C11/4085; G11C8/00; G11C8/04; G11C8/12
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
88 words
A data storage system comprising: (a) an array of memory cells arranged in rows and columns, the cells of each column having a common input/output conductor; (b) first commutator means for successively strobing row conductors of said array for enabling the rows of cells associated with said row conductors to receive and to output data on said common input/output conductors; (c) a bus for transmitting digital data to and from said array; and (d) second commutator means for selectively interconnecting said columns of memory cells with said bus.
Claim 2
Dependent Claim
88 words
A data storage system comprising: (a) an array of memory cells arranged in rows and columns, the cells of each column having a common input/output conductor; (b) first commutator means for successively strobing row conductors of said array for enabling the rows of cells associated with said row conductors to receive and to output data on said common input/output conductors; (c) a bus for transmitting digital data to and from said array; and (d) second commutator means for selectively interconnecting said columns of memory cells with said bus.
Claim 3
Dependent Claim
29 words
The system according to claim 1, wherein said columns of memory cells are arranged in groups and wherein said second commutator means successively interconnects said groups with said bus.
Claim 4
Dependent Claim
37 words
The system according to claim 2 further including control means for adjusting the phase relationship between the strobing of said row conductors and the interconnecting of said groups according to an address received by said control means.
Claim 5
Dependent Claim
66 words
The system according to claim 2, wherein said memory cells comprise random access transistor memory cells and wherein said second commutator means comprises: (a) a shift register having a stage thereof associated with each one of said groups; and (b) a plurality of register selector gates coupled to said shift register for interconnecting said groups with said bus depending on the state of said shift register.
Claim 6
Dependent Claim
26 words
The system according to claim 4, further including control means, responsive to an address received by said system for loading said shift register with binary signals.
Claim 7
Dependent Claim
68 words
The system according to claim 1, wherein said second commutator means comprises: (a) a shift register having a plurality of stages, at least one of said columns of memory cells being associated with each of said stages; and (b) a plurality of register selector gates coupled to said shift register for interconnecting said columns of memory cells with said bus according to the state of said shift register.
Claim 8
Dependent Claim
50 words
The system according to claim 6, further comprising control means, responsive to an address received by said system for loading said shift register with binary signals, said binary signals when being of a predetermined binary state are effective for permitting the transferring of data between said array and said bus.
Claim 9
Dependent Claim
66 words
A data storage system comprising: (a) an array of memory cells arranged in rows and columns; (b) first commutator means for successively strobing the rows of cells to permit the row of cells strobed to store data supplied thereto; (c) a bus for transferring data to said array; and (d) second commutator means for successively coupling the memory cells arranged in said columns to said bus.
Claim 10
Dependent Claim
66 words
A data storage system comprising: (a) an array of memory cells arranged in rows and columns; (b) first commutator means for successively strobing the rows of cells to permit the row of cells strobed to store data supplied thereto; (c) a bus for transferring data to said array; and (d) second commutator means for successively coupling the memory cells arranged in said columns to said bus.
Claim 11
Dependent Claim
49 words
The system according to claim 8, further including control means for adjusting the phase relationship between the strobing of the rows of cells by said first commutator means and the coupling the columns of cells by said second commutator means according to an address received by said control means.
Claim 12
Dependent Claim
70 words
The data storage system according to claim 9, wherein said second commutator means comprises: (a) a shift register having a plurality of stages, at least one of said columns of memory cells being associated with each of said stages; and (b) a plurality of register selector gates coupled to said shift register for interconnecting said columns of memory cells with said bus according to the state of said shift register.
Claim 13
Dependent Claim
34 words
The system according to claim 10, wherein said control means loads said shift register with binary signals, said binary signals being of particular binary states depending upon the address received by said control means.
Claim 14
Dependent Claim
28 words
The system according to claim 9, wherein said control means is coupled to said bus and wherein said address is communicated on said bus to said control means.
Claim 15
Dependent Claim
41 words
The system according to claim 8, wherein said columns of memory cells are arranged in groups for storing bits of data received on said bus in parallel and wherein said second second commutator means successively interconnects said groups with said bus.
Claim 16
Dependent Claim
111 words
A data memory for storing a plurality of words of data received from a bus, said data memory comprising: (a) an array of memory cells arranged in rows and columns, said rows being responsive to a strobe signal for storing data supplied thereto; (b) first means for generating said strobe signal; (c) second means for successively coupling the memory cells arranged in said column to said bus in response to a control signal; and (d) control means for generating said control signal, said control means being responsive to an address received thereby and to said first means for adjusting the timing of said control signal with respect to the strobe signal.
Claim 17
Dependent Claim
111 words
A data memory for storing a plurality of words of data received from a bus, said data memory comprising: (a) an array of memory cells arranged in rows and columns, said rows being responsive to a strobe signal for storing data supplied thereto; (b) first means for generating said strobe signal; (c) second means for successively coupling the memory cells arranged in said column to said bus in response to a control signal; and (d) control means for generating said control signal, said control means being responsive to an address received thereby and to said first means for adjusting the timing of said control signal with respect to the strobe signal.
Claim 18
Dependent Claim
29 words
The data memory according to claim 14, wherein said control means is coupled to said bus and wherein said address is communicated on said bus to said control means.
Claim 19
Dependent Claim
67 words
The system according to claim 14, wherein said second means comprises: (a) a shift register having a plurality of stages, at least one of said columns of memory cells being associated with each of said stages; and (b) a plurality of register selector gates coupled to said shift register for interconnecting said columns of memory cells with said bus according to the state of said shift register.
Claim 20
Dependent Claim
34 words
The system according to claim 16, wherein said control means loads said shift register with binary signals, said binary signals being of particular binary states depending upon the address received by said control means.
Claim 21
Dependent Claim
169 words
A data storage system comprising: (a) an array of memory cells arranged in rows and columns, the cells of a column having input and output conductors common to all cells in a column; (b) first commutator means for successively strobing row conductors of said array for enabling the rows of cells associated with said row conductors to receive and to output data on said input and output conductors; (c) a bus for transmitting digital data to and from said array; (d) second commutator means for interconnecting said columns of memory cells with said bus; and (e) control means for controlling the strobing of said row conductors at the same rate as a bit shifting between the stages of said shift register and for controlling the phase relationship between the strobing of said row conductors and the shifting of said bit in said shift register according to an address received by said system whereby trains of digital data received on said bus are stored in diagonal patterns in said array.
Claim 22
Dependent Claim
169 words
A data storage system comprising: (a) an array of memory cells arranged in rows and columns, the cells of a column having input and output conductors common to all cells in a column; (b) first commutator means for successively strobing row conductors of said array for enabling the rows of cells associated with said row conductors to receive and to output data on said input and output conductors; (c) a bus for transmitting digital data to and from said array; (d) second commutator means for interconnecting said columns of memory cells with said bus; and (e) control means for controlling the strobing of said row conductors at the same rate as a bit shifting between the stages of said shift register and for controlling the phase relationship between the strobing of said row conductors and the shifting of said bit in said shift register according to an address received by said system whereby trains of digital data received on said bus are stored in diagonal patterns in said array.
Claim 23
Dependent Claim
90 words
A data storage system comprising: (a) an array of memory cells arranged in rows and columns; (b) first commutator means for successively strobing the rows of cells to permit the row of cells strobed to store data supplied thereto; (c) a bus for transferring data to said array; and (d) second commutator means for successively coupling the memory cells arranged in said columns to said bus, said first commutator means strobing said rows of cells at the same rate as said second commutator means couples said columns to said bus.
Claim 24
Dependent Claim
90 words
A data storage system comprising: (a) an array of memory cells arranged in rows and columns; (b) first commutator means for successively strobing the rows of cells to permit the row of cells strobed to store data supplied thereto; (c) a bus for transferring data to said array; and (d) second commutator means for successively coupling the memory cells arranged in said columns to said bus, said first commutator means strobing said rows of cells at the same rate as said second commutator means couples said columns to said bus.
Claim 25
Dependent Claim
39 words
The system according to claim 19 wherein said columns of memory cells are arranged in groups for storing bits of data received on said bus in parallel and wherein said commutator means successively interconnects said groups with said bus.
Claim 26
Dependent Claim
135 words
A data memory for storing a plurality of words of data received from a bus, said data memory comprising: (a) an array of memory cells arranged in rows and columns, said rows being responsive to a strobe signal for storing data supplied thereto; (b) first means for generating said strobe signal; (c) second means for successively coupling the memory cells arranged in said column to said bus in response to a control signal; and (d) control means for generating said control signal, said control means being responsive to an address received thereby and to said first means for adjusting the timing of said control signal with respect to the strobe signal, said first commutator means strobing said rows of cells at the same rate as said second commutator means couples said columns to said bus.
Claim 27
Dependent Claim
135 words
A data memory for storing a plurality of words of data received from a bus, said data memory comprising: (a) an array of memory cells arranged in rows and columns, said rows being responsive to a strobe signal for storing data supplied thereto; (b) first means for generating said strobe signal; (c) second means for successively coupling the memory cells arranged in said column to said bus in response to a control signal; and (d) control means for generating said control signal, said control means being responsive to an address received thereby and to said first means for adjusting the timing of said control signal with respect to the strobe signal, said first commutator means strobing said rows of cells at the same rate as said second commutator means couples said columns to said bus.
Claim 28
Dependent Claim
38 words
The system according to claim 21 wherein said columns of memory cells are arranged in groups for storing bits of data on said bus in parallel and wherein said second means successively interconnects said groups with said bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-08-06 | 1983-02-05 | 1983-08-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-08-06 | 1987-02-05 | 1987-08-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-08-06 | 1991-02-05 | 1991-08-07 | $7700.00 | Window Closed / Lapsed |