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US4159214A Expired / Lapsed US ⏱️ 0.0 years remaining

Formation of heterojunctions utilizing back-side surface roughening for stress relief

Assignee: Harris Corp
•
Filing: 1978-05-31
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Granted: 1979-06-26
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Expires: 1998-05-31
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Abstract

Abstract A crack free layer of GaP is epitaxially deposited on a silicon phosphide surface of a silicon substrate having an (III) orientation. The silicon substrate is prebaked on a carbide coated susceptor with palladium diffused hydrogen at about 1200° C. and pretreated with phosphine at about 1140° C. to form the silicon phosphide surface. The temperature is lowered to 800°-900° C. in the presence of phosphine and trimethyl gallium is introduced at a ratio of 1 to 10 with the phosphine. Cracks in the gallium phosphide are prevented by roughing the bottom non-phosphine. Cracks in the silicon substrate such that the roughed surface is under compressive stress and induces tensile stress on the phosphided surface to reduce the compressive stress reduced by gallium phosphide layer when the substrate is annealed at about 1200° C.

Inventors

  • 👤 Donald Mason

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 20:34
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/20; H10P14/32; H10P14/3202; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/34; H10P14/3402; H10P14/3414; H10P14/3418; H10P14/36; H10P14/24; Y; Y10; Y10S; Y10S117/00; Y10S117/913; Y10S438/00; Y10S438/933; Y10S438/938

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 77 words
A method of relieving stress between two layers of different semiconductors, said semiconductors having different coefficients of thermal expansion, comprising roughening the surface of the layer with the lower coefficient of thermal expansion opposite the common surface of said two layers, annealing and cooling said lower coefficient of thermal expansion layer to produce compressive stress on the roughened surface and tensile stress on the common surface, and epitaxially depositing the semiconductor layer with the higher coefficient-of-thermal expansion.
Claim 2
Independent Claim 77 words
A method of relieving stress between two layers of different semiconductors, said semiconductors having different coefficients of thermal expansion, comprising roughening the surface of the layer with the lower coefficient of thermal expansion opposite the common surface of said two layers, annealing and cooling said lower coefficient of thermal expansion layer to produce compressive stress on the roughened surface and tensile stress on the common surface, and epitaxially depositing the semiconductor layer with the higher coefficient-of-thermal expansion.
Claim 3
Dependent Claim 21 words
The method according to claim 1 wherein said annealing is performed before the other layer is deposited at said common surface.
Claim 4
Dependent Claim 22 words
The method according to claim 1 wherein said lower coefficient thermal expansion layer is silicon and said other layer is III-V compound.
Claim 5
Dependent Claim 25 words
The method of claim 3 wherein said silicon is annealed at approximately 1200° C. and said other layer is deposited at 800° to 900° C.
Claim 6
Dependent Claim 12 words
The method of claim 3 wherein said other layer is gallium phosphide.
Claim 7
Dependent Claim 23 words
The method of claim 1 wherein said roughening is performed to produce a damage depth in the range of 15 to 25 microns.

References Cited (Backward Citations)

US3579815A Cited
US3861969A Cited
US3808674A Cited
US3821039A Cited
US3905162A Cited
US3997368A Cited
US4018626A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1982-06-25 1982-12-25 1983-06-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1986-06-25 1986-12-25 1987-06-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1990-06-25 1990-12-25 1991-06-26 $7700.00 Window Closed / Lapsed

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