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US4158882A Expired / Lapsed US ⏱️ 0.0 years remaining

Full-wave rectifier circuit

Assignee: Zenith Electronics LLC
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Filing: 1978-02-27
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Granted: 1979-06-19
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Expires: 1998-02-27
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Abstract

Abstract A full-wave rectifier circuit useful in a low level envelope type video detector or the like comprises a symmetrical network having a pair of input terminals and an output terminal, the output terminal developing a unidirectional flow of current in response to the application of an alternating current signal to at least one of the input terminals. The symmetrical network comprises first and second cross-coupled transistors-current mirror pairs, each transistor being operable for conducting output unidirectional current through its respective current mirror. The current mirrors are connected for responding to the alternating current developed at the input terminals for operating one or the other of the transistors depending upon the relative magnitude of current developed at the two input terminals. The rectifier may be operated from a dual output balanced source of current or, alternatively, in a single ended mode.

Inventors

  • 👤 Richard W. Citta

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 19:03
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/44; H04N5/4446; H02; H02M; H02M7/00; H02M7/02; H02M7/04; H02M7/12; H02M7/21; H02M7/217; H02M7/2173; H03; H03D; H03D1/00; H03D1/14; H03D1/18

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 131 words
A full-wave rectifier circuit comprising: first and second transistors of like conductivity, the collectors of said transistors being connected together forming an output of said rectifier; first and second current mirrors each having an input and an output, the emitters of said first and second transistors being connected for supplying said inputs of said first and second current mirrors respectively and the bases of said first and second transistors being connected to said outputs of said first and second current mirrors respectively; first means coupling the emitter of said first transistor to the base of said second transistor; second means coupling the emitter of said second transistor to the base of said first transistor; and means coupling an alternating current signal to the base of at least one of said transistors.
Claim 2
Dependent Claim 131 words
A full-wave rectifier circuit comprising: first and second transistors of like conductivity, the collectors of said transistors being connected together forming an output of said rectifier; first and second current mirrors each having an input and an output, the emitters of said first and second transistors being connected for supplying said inputs of said first and second current mirrors respectively and the bases of said first and second transistors being connected to said outputs of said first and second current mirrors respectively; first means coupling the emitter of said first transistor to the base of said second transistor; second means coupling the emitter of said second transistor to the base of said first transistor; and means coupling an alternating current signal to the base of at least one of said transistors.
Claim 3
Dependent Claim 17 words
The full-wave rectifier according to claim 1 wherein said first and second means each comprise resistive means.
Claim 4
Dependent Claim 35 words
The full-wave rectifier according to claim 1 including a signal source developing a pair of differential output alternating current signals, each of said output signals being coupled to the base of one of said transistors.
Claim 5
Dependent Claim 50 words
The full-wave rectifier according to claim 1 including first and second sources of DC bias current each connected for supplying the base of one of said transistors and a signal source developing an output alternating current connected in series aiding relationship with one of said sources of DC bias current.

References Cited (Backward Citations)

US3805093A Cited
US3970870A Cited
US4004247A Cited
US4004161A Cited
US4053796A Cited
US4069460A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1982-06-18 1982-12-18 1983-06-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1986-06-18 1986-12-18 1987-06-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1990-06-18 1990-12-18 1991-06-19 $7700.00 Window Closed / Lapsed

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