US3970870A
Expired / Lapsed
US
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Signal rectifying circuit
Assignee: Sony Corp
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Filing: 1974-11-14
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Granted: 1976-07-20
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Expires: 1994-11-14
Abstract
Abstract A signal rectifying circuit which is capable of providing rectification either with a balanced or unbalanced input and wherein the output comprises an undelayed signal. A pair of transistors of opposite type are coupled to the input circuit such that they alternately conduct with the positive and negative half cycles of the input signal and wherein a third transistor is coupled to the pair of input transistors such that it conducts during both the positive and negative portions of the input wave so as to provide a rectified output signal. A second embodiment provides a pair of diodes interconnected with the rectifying circuit so as to remove the time delay normally resulting due to the voltage required to bias a transistor to conduction.
Inventors
- 👤 Tetsuya Horichi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 22:49
CPC Classifications
H; H03; H03D; H03D1/00; H03D1/14; H03D1/18; G; G01; G01R; G01R19/00; G01R19/22
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
138 words
A signal rectifying circuit adapted for rectifying an input terminal signal having first and second polarity cycles with respect to a reference terminal, comprising: a. an input terminal; b. a reference terminal; c. a first signal input means connected between the input and reference terminals for inverting at least a portion of the first polarity signal cycle; d. a second signal input means connected between the input and reference terminals for inverting at least a portion of the second polarity signal cycle; e. a signal inversion means connected to said second signal input means for further inverting at least a portion of said second polarity signal cycle; and f. an output signal means connected to both said first signal input means and signal inversion means for providing a rectified output between an output terminal and said reference terminal.
Claim 2
Dependent Claim
138 words
A signal rectifying circuit adapted for rectifying an input terminal signal having first and second polarity cycles with respect to a reference terminal, comprising: a. an input terminal; b. a reference terminal; c. a first signal input means connected between the input and reference terminals for inverting at least a portion of the first polarity signal cycle; d. a second signal input means connected between the input and reference terminals for inverting at least a portion of the second polarity signal cycle; e. a signal inversion means connected to said second signal input means for further inverting at least a portion of said second polarity signal cycle; and f. an output signal means connected to both said first signal input means and signal inversion means for providing a rectified output between an output terminal and said reference terminal.
Claim 3
Dependent Claim
63 words
The signal rectifying circuit of claim 1 in which said first and second signal input means comprise transistor devices of opposite polarity types, said signal inversion means comprises a transistor device of the same polarity as said first input means transistor device, and said output signal means comprises a transistor device of the same polarity as said second signal input means transistor device.
Claim 4
Dependent Claim
31 words
The signal rectifying circuit of claim 1 in which a low impedance output means is connected to said output signal means to lower the output impedance from said signal rectifying circuit.
Claim 5
Dependent Claim
32 words
The signal rectifying circuit of claim 1 in which semiconductor device means are connected to said signal inversion means and output signal means for preventing signal clipping in said latter two means.
Claim 6
Dependent Claim
38 words
The signal rectifying circuit of claim 1 which further includes biasing means connected to each of said first and second input circuit means to permit inversion of substantially all of said first and second polarity signal cycles, respectively.
Claim 7
Dependent Claim
44 words
The signal rectifying circuit of claim 5 which include a pair of unilateral current devices connected to said biasing means and to said first and second signal input means to provide invention of substantially all of said first and second polarity signal cycles, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-07-20 | 1980-01-19 | 1980-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-07-20 | 1984-01-19 | 1984-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-07-20 | 1988-01-19 | 1988-07-20 | $7700.00 | Window Closed / Lapsed |