Patent US2157952A successfully refreshed from Google Patents.
Patent US4156246A successfully refreshed from Google Patents.
US4156246A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Combined ohmic and Schottky output transistors for logic circuit
Assignee: AT&T Inc
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Filing: 1977-05-25
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Granted: 1979-05-22
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Expires: 1997-05-25
Abstract
Abstract A silicon semiconductor integrated logic circuit of the injection or merged transistor logic type has output contacts in which ohmic and Schottky barrier portions are combined. A portion of the surface region of each output transistor collector is converted to more heavily doped N-type conductivity so that a metal contact applied thereto makes low resistance contact to the more heavily doped portions but forms a contact of the Schottky barrier type to the more lightly doped portion. The effect of the Schottky contact portion is to control minority carrier storage in the collector of the NPN output transistor by forcing the hole excess density at the Schottky portion surface to be zero thereby enabling short propagation delay time.
Inventors
- 👤 Richard A. Pedersen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 22:16
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/20; H10D64/23; H10D64/231; H10D62/00; H10D62/10; H10D62/13; H10D62/137; H10D84/00; H10D84/60; H10D84/65
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
173 words
A semiconductor integrated circuit device of the merged transistor logic type in which the output transistor is of the NPN type comprising a body of semiconductor material having a major surface, a first zone of N-type conductivity in a portion of said body contiguous with a portion of said major surface and constituting the collector zone of said output transistor, said first zone having a net impurity concentration of 1-5×10 16 atoms/cc, a second zone of N-type conductivity within said first zone and contiguous with a portion of said major surface, said second zone having a net impurity concentration greater than 10 19 atoms/cc, and having a lesser depth from said major surface than said first zone, the area of said first zone portion contiguous with said major surface being about four times the area of said second zone contiguous with said major surface, and a metallic layer, selected from the group consisting of platinum silicide and aluminum, on said major surface only on the portions contiguous with said first and second zones.
Claim 2
Dependent Claim
173 words
A semiconductor integrated circuit device of the merged transistor logic type in which the output transistor is of the NPN type comprising a body of semiconductor material having a major surface, a first zone of N-type conductivity in a portion of said body contiguous with a portion of said major surface and constituting the collector zone of said output transistor, said first zone having a net impurity concentration of 1-5×10 16 atoms/cc, a second zone of N-type conductivity within said first zone and contiguous with a portion of said major surface, said second zone having a net impurity concentration greater than 10 19 atoms/cc, and having a lesser depth from said major surface than said first zone, the area of said first zone portion contiguous with said major surface being about four times the area of said second zone contiguous with said major surface, and a metallic layer, selected from the group consisting of platinum silicide and aluminum, on said major surface only on the portions contiguous with said first and second zones.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-05-21 | 1982-11-20 | 1983-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-05-21 | 1986-11-20 | 1987-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-05-21 | 1990-11-20 | 1991-05-22 | $7700.00 | Window Closed / Lapsed |