Digital data change-of-state detector

Claim 1

An electronic circuit that detects changes in digital data that occurs on a parallel data bus, said electronic circuit comprising: a. a memory register that stores digital data that enters said register on parallel lines, and exits said register on parallel lines when said register receives a strobe input; b. a plurality of comparison means connected in parallel and coupled to said memory register, each one of said parallel lines being coupled to a different said comparison means for comparing the input and output data that enters and exits said memory register; each of said comparison means comprises: an AND gate whose inputs are coupled to a parallel input of said memory register and a parallel output of said register; a first NOR gate whose inputs are coupled to said parallel input of said memory register and said parallel output of said register; and a second NOR gate whose inputs are coupled to the output of said AND gate and the output of said first NOR gate; c. an OR gate whose input is coupled to the output of each of said second NOR gates; and d. a monostable flip flop whose input is coupled to the output of said OR gate and whose output is coupled to the strobe input of said register, whereby if the input digital data to said register is different from the output digital data of said register one or more of said comparison means will generate a signal causing the data on the inputs of said register to be stored in said register, signifying that the data has changed state.