Voltage controlled attenuator

Claim 2

A voltage controlled attenuator comprising: a pair of gain cells each being directly fed by an actively linearized current source adapted to receive an input signal, said gain cells being controlled by a single gain control voltage, a pair of linearized buffer amplifiers each having an actively linearized current source and connected to the output of each of said gain cells for linear operation over a wide range of DC quiescent input operating conditions and minimizing loading on said gain cells, and a differential output amplifier being fed by said buffer amplifiers for generating an output signal whereby the effect of control voltage in the output signal and any DC shift caused by changes in control voltage and remaining distortion products are removed.

Claim 3

A voltage controlled attenuator according to claim 1 in which said pair of gain cells each have a pair of transistors with base, emitter and collector, each pair of transistors having said emitters connected directly together and each pair of emitters fed by said separate linearized current source.

Claim 4

A voltage controlled attenuator according to claim 2 in which said voltage controlled attenuator includes multiple parallel transistors for maintaining low current densities.

Claim 5

A voltage controlled attenuator according to claim 2 in which said voltage controlled attenuator includes large geometry transistors for maintaining low current densities and low circuit impedances.

Claim 6

A voltage controlled attenuator comprising: a pair of gain cells each being directly fed by a linearized current source adapted to receive an input signal, said pair of gain cells each have a pair of transistors with base, emitter and collector, each pair of transistors having said emitters connected directly together and each pair of emitters fed by said separate linearized current source, a pair of linearized buffer amplifiers each having a linearized current source and connected to the output of each of said gain cells for linear operation over a wide range of DC quiescent input operating conditions and minimizing loading on said gain cells, one transistor of each pair has the base and collector directly connected together and directly to signal ground and in which a resistor is connected from the collectors of said other transistor in each pair to a voltage source thereby developing signal voltages across each transistor that are fed to the linearized buffer amplifiers for maintaining appropriate loading on the gain cells and minimizing the loading effect of the differential output amplifier, and a differential output amplifier being fed by said buffer amplifiers for generating an output signal whereby the effect of control voltage in the output signal and any DC shift caused by changes in control voltage and remaining distortion products are removed.

Claim 7

A voltage controlled attenuator comprising: a pair of gain cells each being directly fed by a linearized current source adapted to receive an input signal, said pair of gain cells each have a pair of transistors with base, emitter and collector, each pair of transistors having said emitters connected directly together and each pair of emitters fed by said separate linearized current source, a pair of linearized buffer amplifiers each having a linearized current source and connected to the output of each of said gain cells for linear operation over a wide range of DC quiescent input operating conditions and minimizing loading on said gain cells, one transistor of each pair has the base and collector directly connected together and directly to signal ground and in which a resistor is connected from the collectors of said other transistor in each pair to a voltage source thereby developing signal voltages across each transistor that are fed to the linearized buffer amplifiers for maintaining appropriate loading on the gain cells and minimizing the loading effect of the differential output amplifier, and a differential output amplifier being fed by said buffer amplifiers for generating an output signal whereby the effect of control voltage in the output signal and any DC shift caused by changes in control voltage and remaining distortion products are removed.

Claim 8

A voltage controlled attenuator comprising: a pair of gain cells having low current densities and low circuit impedances each being directly fed by a linearized current source adapted to receive an input signal, said gain cells being controlled by a single gain control voltage, a pair of linearized buffer amplifiers each connected to the output of one of said gain cells for minimizing loading on said gain cells, said pair of linearized current sources are each common base amblifiers fed by an inverted and a non-inverted signal source respectively and having a second inverting amplifier in feedback between emitter and base, and a differential output amplifier being fed by said buffer amplifiers for generating an output signal whereby the effect of control voltage in the output signal and any DC shift caused by changes in control voltage and remaining distortion products are removed.

Claim 9

A voltage controlled attenuator comprising: a pair of gain cells having low current densities and low circuit impedances each being directly fed by a linearized current source adapted to receive an input signal, said gain cells being controlled by a single gain control voltage, a pair of linearized buffer amplifiers each connected to the output of one of said gain cells for minimizing loading on said gain cells, said pair of linearized current sources are each common base amblifiers fed by an inverted and a non-inverted signal source respectively and having a second inverting amplifier in feedback between emitter and base, and a differential output amplifier being fed by said buffer amplifiers for generating an output signal whereby the effect of control voltage in the output signal and any DC shift caused by changes in control voltage and remaining distortion products are removed.

Claim 10

A voltage controlled attenuator comprising: a pair of gain cells having low current densities and low circuit impedances each being directly fed by a linearized current source adapted to receive an input signal, said gain cells being controlled by a single gain control voltage, a pair of linearized buffer amplifiers each connected to the output of one of said gain cells for minimizing loading on said gain cells, said gain cells include multiple parallel transistors for maintaining low current densities and low circuit impedances, and a differential output amplifier being fed by said buffer amplifiers for generating an output signal whereby the effect of control voltage in the output signal and any DC shift caused by changes in control voltage and remaining distortion products are removed.

Claim 11

A voltage controlled attenuator comprising: a pair of gain cells having low current densities and low circuit impedances each being directly fed by a linearized current source adapted to receive an input signal, said gain cells being controlled by a single gain control voltage, a pair of linearized buffer amplifiers each connected to the output of one of said gain cells for minimizing loading on said gain cells, said gain cells include multiple parallel transistors for maintaining low current densities and low circuit impedances, and a differential output amplifier being fed by said buffer amplifiers for generating an output signal whereby the effect of control voltage in the output signal and any DC shift caused by changes in control voltage and remaining distortion products are removed.

Claim 12

A voltage controlled attenuator comprising: a pair of gain cells each being directly fed by a linearized current source adapted to receive an input signal, said gain cells include large geometry transistors for maintaining low circuit densities and low circuit impedances, said gain cells being controlled by a single gain control voltage, a pair of linearized buffer emplifiers each having a linearized current source and connected to the output of each of said gain cells for linear operation over a wide range of DC quiescent input operating conditions and minimizing loading on said gain cells, and a differential output amplifier being fed by said buffer amplifiers for generating an output signal whereby the effect of control voltage in the output signal and any DC shift caused by changes in control voltage and remaining distortion products are removed.

Claim 13

A voltage controlled attenuator comprising: a pair of gain cells each being directly fed by a linearized current source adapted to receive an input signal, said gain cells include large geometry transistors for maintaining low circuit densities and low circuit impedances, said gain cells being controlled by a single gain control voltage, a pair of linearized buffer emplifiers each having a linearized current source and connected to the output of each of said gain cells for linear operation over a wide range of DC quiescent input operating conditions and minimizing loading on said gain cells, and a differential output amplifier being fed by said buffer amplifiers for generating an output signal whereby the effect of control voltage in the output signal and any DC shift caused by changes in control voltage and remaining distortion products are removed.

Claim 14

A voltage controlled attenuator comprising, a pair of gain cells each having a pair of transistors with base, emitter and collector, each pair of transistors having said emitters connected directly together and each pair of emitters directly fed by a separate current source adapted to receive an input signal, one transistor of each pair having the base and collector connected directly together and to signal ground, the base of said other transistor of each pair being connected directly together and fed by a single gain control voltage, a separate resistor connected from each of the collectors of said other transistors in each pair to a voltage source thereby developing output signal voltages across each resistor, and a buffered differential amplifier connected across each resistor for generating an output signal whereby loading of the gain cells is minimized and the effect of control voltage and distortion in the output signal and any DC shift caused by changes in control voltage is removed.

Claim 15

A voltage controlled attenuator comprising, a pair of gain cells each having a pair of transistors with base, emitter and collector, each pair of transistors having said emitters connected directly together and each pair of emitters directly fed by a separate current source adapted to receive an input signal, one transistor of each pair having the base and collector connected directly together and to signal ground, the base of said other transistor of each pair being connected directly together and fed by a single gain control voltage, a separate resistor connected from each of the collectors of said other transistors in each pair to a voltage source thereby developing output signal voltages across each resistor, and a buffered differential amplifier connected across each resistor for generating an output signal whereby loading of the gain cells is minimized and the effect of control voltage and distortion in the output signal and any DC shift caused by changes in control voltage is removed.

Claim 16

A gain cell comprising two pairs of multiple parallel transistors for maintaining low current densities each transistor having a base, emitter and collector, each pair of transistors having said emitters connected together and each pair of emitters adapted to be directly fed by a separate current source, one transistor of each pair having the base and collector connected together to ground and to each other, the base of said outer transistor of each pair being connected together and fed by a single gain control voltage, a separate resistor connected from each of the collectors of said other transistors in each pair of a voltage source thereby developing output signals across each resistor, and a linearized buffer amplifier connected across each resistor for maintaining appropriate loading on the gain cells and extending the undistorted output range of the buffer amplifier.

Claim 17

A gain cell comprising two pairs of multiple parallel transistors for maintaining low current densities each transistor having a base, emitter and collector, each pair of transistors having said emitters connected together and each pair of emitters adapted to be directly fed by a separate current source, one transistor of each pair having the base and collector connected together to ground and to each other, the base of said outer transistor of each pair being connected together and fed by a single gain control voltage, a separate resistor connected from each of the collectors of said other transistors in each pair of a voltage source thereby developing output signals across each resistor, and a linearized buffer amplifier connected across each resistor for maintaining appropriate loading on the gain cells and extending the undistorted output range of the buffer amplifier.

Claim 18

A gain cell comprising, two pairs of large geometry transistors for maintaining low current densities and low current impedances each having a base, emitter and collector, each pair of transistors having said emitters connected together and each pair of emitters adapted to be directly fed by a separate current source, one transistor of each pair having the base and collector connected together to ground and to each other, the base of said other transistor of each pair being connected together and fed by a single gain control voltage, a separate resistor connected from each of the collectors of said other transistors in each pair to a voltage source thereby developing output signals across each resistor, and a linearized buffer amplifier connected across each resistor for maintaining appropriate loading on the gain cells and extending the undistorted output range of the buffer amplifier.

Claim 19

A gain cell comprising, two pairs of large geometry transistors for maintaining low current densities and low current impedances each having a base, emitter and collector, each pair of transistors having said emitters connected together and each pair of emitters adapted to be directly fed by a separate current source, one transistor of each pair having the base and collector connected together to ground and to each other, the base of said other transistor of each pair being connected together and fed by a single gain control voltage, a separate resistor connected from each of the collectors of said other transistors in each pair to a voltage source thereby developing output signals across each resistor, and a linearized buffer amplifier connected across each resistor for maintaining appropriate loading on the gain cells and extending the undistorted output range of the buffer amplifier.