US3757240A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Active attenuator
Assignee: HP Inc
•
Filing: 1972-03-15
•
Granted: 1973-09-04
•
Expires: 1992-03-15
Abstract
Abstract A variable attenuator includes active elements for providing the desired attenuation with good pulse response. Each of the transistors in the circuit is included in a current-splitting network which assures that the power dissipation remains the same, regardless of the attenuation setting.
Inventors
- 👤 O Fogg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:51
CPC Classifications
H; H03; H03G; H03G1/00; H03G1/0005; H03G1/0035; H03H; H03H11/00; H03H11/02; H03H11/24
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
203 words
Signal translating circuit comprising: first, second, third and fourth transistors, each having emitter, base and collector electrodes; means connecting the emitter electrodes of the first and second transistors to receive a first input signal; means connecting the emitter electrodes of the third and fourth transistors to receive a second input signal; first supply means connected to supply bias signal to the collector electrodes of the first and fourth transistors; second supply means connected to supply bias signal to the base electrodes of the first and fourth transistors; third supply means connected to supply bias signal of selectable magnitude to the base electrodes of the second and third transistors; and output means connected to the collector electrodes of the second and third transistors for supplying bias signals thereto to establish on said collector electrodes collector voltages which are substantially equal independently of the magnitudes of currents in said collector electrodes as said currents vary, said output means producing from said collector currents first and second output signals representative of the first and second input signals altered in amplitude by an amount determined by the magnitude of bias signal applied to the base electrodes of the second and third transistors by said third supply means.
Claim 2
Dependent Claim
203 words
Signal translating circuit comprising: first, second, third and fourth transistors, each having emitter, base and collector electrodes; means connecting the emitter electrodes of the first and second transistors to receive a first input signal; means connecting the emitter electrodes of the third and fourth transistors to receive a second input signal; first supply means connected to supply bias signal to the collector electrodes of the first and fourth transistors; second supply means connected to supply bias signal to the base electrodes of the first and fourth transistors; third supply means connected to supply bias signal of selectable magnitude to the base electrodes of the second and third transistors; and output means connected to the collector electrodes of the second and third transistors for supplying bias signals thereto to establish on said collector electrodes collector voltages which are substantially equal independently of the magnitudes of currents in said collector electrodes as said currents vary, said output means producing from said collector currents first and second output signals representative of the first and second input signals altered in amplitude by an amount determined by the magnitude of bias signal applied to the base electrodes of the second and third transistors by said third supply means.
Claim 3
Dependent Claim
82 words
Signal translating circuit as in claim 1 wherein: said output means includes a pair of transistors having collector and base electrodes and having emitter electrodes connected in common as a differential amplifier having an input circuit including said base electrodes connected to the collector electrodes of said second and third transistors and providing said first and second output signals at the collector electrodes thereof; and each of said pair of transistors includes feedback resistors connected between the respective collector and base electrodes.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-03 | 1977-03-05 | 1977-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-03 | 1981-03-05 | 1981-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-03 | 1985-03-05 | 1985-09-04 | $7700.00 | Window Closed / Lapsed |