Patent US4153943A successfully refreshed from Google Patents.
US4153943A
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High speed I/O for content addressable type memories
Assignee: Honeywell Inc
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Filing: 1977-08-12
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Granted: 1979-05-08
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Expires: 1997-08-12
Abstract
Abstract A multiple path input/output switching circuit particularly adapted for use with a serially accessed content addressable memory where several simultaneous data transfers may be carried out between the memory and a host system.
Inventors
- 👤 George A. Anderson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:55
CPC Classifications
G; G06; G06F; G06F16/00; G06F16/90; G06F16/903; G06F16/90335; G06F16/90339
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
285 words
A data switching system having the internal capacity to selectively connect each of a plurality of input/output lines on one side of the system to any one of a plurality of available input/output lines on another side of the system, said system comprising: N word input/output lines where N is greater than 1; M data input/output lines where M is greater than 1 and M≦N; request means for selecting n word input/output lines for data transfer, where 0≦n≦N; switching means for connecting each of the n selected word input/output lines to one of n data input/output lines to permit parallel data transfer, said switching means comprising an array of switching circuits having N rows and M columns with each switching circuit being positioned at the intersection of each row and column and where the word input/output and request signals are connected to one end of the switching circuits of each row, and the data input/output lines are connected to one end of the switching circuits of each column; enable means for indicating to the switching means the identity of the first data input/output line to which one of the word input/output lines may be connected, said enable means being connected to one end of the switching circuits of each column; means for propagating a request signal along a row until the request signal reaches a switching circuit intersection at which the enable signal is present; means for propagating the enable signal along a column until it reaches an intersection at which a request signal is present; and means for connecting a word input/output line and the data input/output line corresponding to the switching intersection at which the enable signal and a request signal are present.
Claim 2
Dependent Claim
285 words
A data switching system having the internal capacity to selectively connect each of a plurality of input/output lines on one side of the system to any one of a plurality of available input/output lines on another side of the system, said system comprising: N word input/output lines where N is greater than 1; M data input/output lines where M is greater than 1 and M≦N; request means for selecting n word input/output lines for data transfer, where 0≦n≦N; switching means for connecting each of the n selected word input/output lines to one of n data input/output lines to permit parallel data transfer, said switching means comprising an array of switching circuits having N rows and M columns with each switching circuit being positioned at the intersection of each row and column and where the word input/output and request signals are connected to one end of the switching circuits of each row, and the data input/output lines are connected to one end of the switching circuits of each column; enable means for indicating to the switching means the identity of the first data input/output line to which one of the word input/output lines may be connected, said enable means being connected to one end of the switching circuits of each column; means for propagating a request signal along a row until the request signal reaches a switching circuit intersection at which the enable signal is present; means for propagating the enable signal along a column until it reaches an intersection at which a request signal is present; and means for connecting a word input/output line and the data input/output line corresponding to the switching intersection at which the enable signal and a request signal are present.
Claim 3
Dependent Claim
54 words
The invention as claimed in claim 1 wherein each switching circuit comprises: means for propagating the enabling signal diagonally from the switching circuit to a switching circuit at the next row and column in the event that the enable signal and a request signal are present at the switching intersection associated with switching circuit.
Claim 4
Dependent Claim
197 words
A memory system comprising: N word storage means where N is greater than 1; N word input/output lines connected to the N word storage means; M data input/output lines for transmitting data to or from the memory system; request means for providing request signals indicative of the word input/output lines selected for data transfer; control logic means for providing an enable signal indicative of the identity of the first available data input/output line to which one of the selected word input/output lines may be connected; switching means comprising an array of switching circuits connected to the N word input/output lines and the M data input/output lines for receiving the request signals and the enable signal and connecting the selected word input/output lines to data input/output lines to permit parallel data transfer; said array of switching circuits comprising: word interface logic circuit blocks connected to the word input/output lines; data line interface logic circuit blocks connected to the data input/output lines; and a matrix of connection circuit blocks for connecting the selected word input/output lines to data input/output lines, the matrix being connected between the word interface logic circuit blocks and the data line interface logic circuit blocks.
Claim 5
Dependent Claim
197 words
A memory system comprising: N word storage means where N is greater than 1; N word input/output lines connected to the N word storage means; M data input/output lines for transmitting data to or from the memory system; request means for providing request signals indicative of the word input/output lines selected for data transfer; control logic means for providing an enable signal indicative of the identity of the first available data input/output line to which one of the selected word input/output lines may be connected; switching means comprising an array of switching circuits connected to the N word input/output lines and the M data input/output lines for receiving the request signals and the enable signal and connecting the selected word input/output lines to data input/output lines to permit parallel data transfer; said array of switching circuits comprising: word interface logic circuit blocks connected to the word input/output lines; data line interface logic circuit blocks connected to the data input/output lines; and a matrix of connection circuit blocks for connecting the selected word input/output lines to data input/output lines, the matrix being connected between the word interface logic circuit blocks and the data line interface logic circuit blocks.
Claim 6
Dependent Claim
116 words
The memory system of claim 3 wherein each connection logic block comprises: means for propagating a request signal along a row until the request signal reaches a switching intersection at which the enable signal is present; means for propagating the enable signal along a column until it reaches an intersection at which a request signal is present; means for connecting the word input/output line and the data input/output line corresponding to the switching intersection at which the enable signal and a request signal are present; and means for propagating the enable signal diagonally to the next row and column in the event that the enable signal and a request signal are present at the switching intersection.
Claim 7
Dependent Claim
28 words
The memory system of claim 3 wherein the switching means generates a Match Count signal indicative of the number of data input/output lines required by the switching means.
Claim 8
Dependent Claim
42 words
The memory system of claim 5 wherein the control logic means receives a Match Count In signal and wherein the enable signal indicative of the identity of the first available data input/output line is a function of the Match Count In signal.
Claim 9
Dependent Claim
46 words
The memory system of claim 6 wherein the control logic means receives the Match Count signal from the switching means and provides a Match Count Out signal which is a function of the Match Count In signal and the Match Count signal from the switching means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-05-07 | 1982-11-06 | 1983-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-05-07 | 1986-11-06 | 1987-05-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-05-07 | 1990-11-06 | 1991-05-08 | $7700.00 | Window Closed / Lapsed |