Transition coding method for synchronous binary information and encoder and decoder employing the method

Claim 3

A coding device for synchronous binary data timed by a frequency F, which is controlled by clock signal H at frequency F defining a bit-time of duration 1/F for each bit and applying the coding procedure of claim 1, said device comprising a first means receiving the said binary data and the clock signal H to provide a first two-level signal having a level transition in the middle of each bit-time for which the data has the first said given value, second means receiving the said data and the clock signal H and providing a second two-level signal having a level transition at the beginning of each bit-time for which the data has the second said given value, third means receiving the said first signal to provide a third two-level signal which changes level at each transition of a first level to a second level of the said first signal, fourth means receiving the said second signal and controlled by the said first means to provide a fourth two-level signal which changes level at each transition of the second signal which occurs while the said first signal is at the said first level and also one half period 1/2 F after each transition of the second signal which occurs when the first signal is at the said second level, and fifth means receiving the said third and the said fourth signals to provide a two-level signal having a level transition at each transition at each of the said third and fourth signals.

Claim 4

A coding device according to claim 2 wherein the said fifth means is formed by an EXCLUSIVE OR gate.

Claim 5

A coding device according to claim 2 wherein the said clock signal H has a form factor 1/2, the said fourth means comprises means for phase modulating the clock signal H with the first signal, and a sampling and blocking flip-flop sampling the said second signal under the control of the modulated clock signal and delivering the said fourth signal.

Claim 6

A coding device according to claim 2 wherein the said third means comprises a D type flip-flop clocked by the said first signal and whose inverted ouput is fed back to its D input.

Claim 7

A coding device according to claim 2 wherein the said data is in the form of an NRZ signal, the said first means comprising a J-K type flip-flop receiving the said NRZ signal on its J and K inputs and clocked by the clock signal H to change in the middle of each bit period for which the data has the said first value, and the said second means comprises a JK flip-flop receiving the inverted NRZ signal on its J and K inputs and clocked by the clock signal to change state at the beginnings of the bit periods for which the data has the said second value.

Claim 8

A device for the decoding of signal resulting from encoding according to the process according to claim 1, of synchronous binary information timed at frequency F, and comprising a transition detector for detection of the transitions in the signal to be decoded, a local clock comprising a voltage driven oscillator, said clock delivering a signal Hr at frequency F and composed of alternating pulses of a first and second level, each of 1/2.F duration; A first means connected to said detector and receiving said signal Hr to deliver a pulse I of 1/2.F duration following each transition in the signal for decoding which has occured when signal Hr was at a given level of the two said levels; a second means for phase modulation of said signal Hr by means of signal S, the latter consisting of a string of pulses I, the modulated signal delivered by said second means being filtered by a low-pass filter before application in control of said oscillator, so that said given levels of signal Hr will be centered on transitions situated at the center of bit-times in the signal to be decoded; a sampling-rejecting circuit receiving signal S and controlled by the edges of the Hr signal going from said stated level to the other level; a third means clocked by Hr to detect the transitions in the output signal of said sampling-rejecting circuit and to deliver a bit of said first or said second value, at each period of signal Hr, according to whether the output of said sampling-rejecting circuit has or does not have a transition at the start of said period of signal Hr.

Claim 9

A coding device according to claim 7, possessing the feature that said transition detector delivers a brief output pulse, termed a "transition" pulse, in response to each transition in the input message, and that said first means comprises a gate for selection amongst all the transition pulses of those which occur while signal Hr is at said given level, plus a one shot multivibrator to extend the transition pulses so selected in duration to 1/2.F.

Claim 10

A decoding device according to claim 7, wherein said second means comprises an exclusive OR gate.

Claim 11

A decoding device according to claim 7, wherein said third means comprises a device which delays the output signal of the sampling-rejecting circuit by one period of signal Hr, and a device for comparison of the levels of said delayed signal and the undelayed output of said sampling-rejecting circuit.

Claim 12

A binary data transmission equipment an encoding device in the transmitting terminal for transformation of said binary data into a coded signal, and a decoding device at the receiving terminal, to decode the coded signal received, said encoding device being in accordance with claims 2, and possessing the features that the decoding device comprises a transition detector for detection of the transitions in a signal to be decoded, a local clock including a voltage-driven oscillator, said clock delivering a signal Hr at frequency F and in the form of alternating bidirectional pulses defining a first and a second level, each of duration 1/2.F, a first means connected to said detector and receiving said signal Hr, to deliver a pulse I of duration 1/2.F following each transition in the signal to be decoded that occured when signal Hr was at a given level of its two levels, a second means for phase-modulation of said signal Hr by means of signal S, the latter consisting of the series of pulses, I the modulated signal delivered by said second means being filtered through a low-pass filter and applied in control of said oscillator, so that said given levels of signal Hr will be centered on transitions occuring at the center of bit-time in the signal to be decoded; a sampling-rejecting circuit receiving signal S and responding to the edges of signal Hr pulses going from said given level to the other level; a third means clocked by signal Hr and detecting the transitions in the sampling-rejecting circuits output signal so as to deliver, in coincidence with each period of signal Hr, a bit of said first or second value, according to whether the output signal of the sampling-rejecting circuit has or does not have a transition at the start of said period of signal Hr.