Patent EP0146478A2 successfully refreshed from Google Patents.
Patent US4151377A successfully refreshed from Google Patents.
US4151377A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High impedance loop-seizing and dial pulsing circuit
Assignee: Nokia of America Corp
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Filing: 1978-01-03
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Granted: 1979-04-24
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Expires: 1998-01-03
Abstract
Abstract An improved loop-seizing and dial pulsing circuit arrangement of the type employed in telephone trunks has an extremely low insertion loss. The circuit comprises a diode bridge connected across a telephone loop and a controlled constant current source connected across the bridge. A current limiting diode also referred to as a constant current diode is used to establish a bias current for the constant current source.
Inventors
- 👤 Donald E. Whitaker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:40
CPC Classifications
H; H04; H04M; H04M3/00; H04M3/22; H04M3/2272
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
56 words
In a loop-seizing circuit comprising: a plurality of diodes arranged as a bridge; a constant current source connected across said diode bridge, said constant current source comprising a transistor having a biasing terminal; the improvement comprising: a constant current diode having first circuit connections to said diode bridge and second circuit connections to said biasing terminal.
Claim 2
Dependent Claim
56 words
In a loop-seizing circuit comprising: a plurality of diodes arranged as a bridge; a constant current source connected across said diode bridge, said constant current source comprising a transistor having a biasing terminal; the improvement comprising: a constant current diode having first circuit connections to said diode bridge and second circuit connections to said biasing terminal.
Claim 3
Dependent Claim
27 words
A loop-seizing circuit according to claim 1 further comprising controlled switching means connected to said constant current diode for selectively enabling and disabling said constant current source.
Claim 4
Dependent Claim
23 words
A loop-seizing circuit according to claim 2 wherein said controlled switching means includes an optical isolator serially connected to said constant current source.
Claim 5
Dependent Claim
28 words
A loop-seizing circuit according to claim 1 further comprising an optical isolator serially connected between two of such plurality of diodes for generating a reverse battery indication signal.
Claim 6
Dependent Claim
123 words
In a loop-seizing circuit comprising: first, second, third and fourth terminals; first, second, third and fourth diode means each respectively connected between said first and second terminals, said second and third terminals, said third and fourth terminals, and said fourth and first terminals; a constant current source connected between said first and third terminals, said constant current source comprising a transistor having a first, second, and base leads, first means for connecting said first lead to said first terminal and second means for connecting said second lead to said third terminal; the improvement comprising: a constant current diode; third means for connecting said constant current diode to said first terminal; and fourth means for connecting said constant current diode to said base lead.
Claim 7
Dependent Claim
123 words
In a loop-seizing circuit comprising: first, second, third and fourth terminals; first, second, third and fourth diode means each respectively connected between said first and second terminals, said second and third terminals, said third and fourth terminals, and said fourth and first terminals; a constant current source connected between said first and third terminals, said constant current source comprising a transistor having a first, second, and base leads, first means for connecting said first lead to said first terminal and second means for connecting said second lead to said third terminal; the improvement comprising: a constant current diode; third means for connecting said constant current diode to said first terminal; and fourth means for connecting said constant current diode to said base lead.
Claim 8
Dependent Claim
21 words
A loop-seizing circuit according to claim 5 further comprising: controlled switching means for selectively enabling and disabling said constant current source.
Claim 9
Dependent Claim
23 words
A loop-seizing circuit according to claim 6 wherein said controlled switching means includes an optical isolator serially connected to said constant current diode.
Claim 10
Dependent Claim
67 words
A loop-seizing circuit according to claim 5 wherein said constant current source further comprises a second transistor having first, second and base leads; fifth means for connecting said second transistor first lead to said first transistor base lead; sixth means for connecting said second transistor second lead to said third terminal; and seventh means for connecting said second transistor base lead to said first transistor second lead.
Claim 11
Dependent Claim
21 words
A loop-seizing circuit according to claim 8 further comprising: controlled switching means for selectively enabling and disabling said constant current source.
Claim 12
Dependent Claim
23 words
A loop-seizing circuit according to claim 9 wherein said controlled switching means includes an optical isolator serially connected to said constant current diode.
Claim 13
Dependent Claim
23 words
A loop-seizing circuit according to claim 9 wherein said second means includes a first resistor and said seventh means comprises a second resistor.
Claim 14
Dependent Claim
20 words
A loop-seizing circuit according to claim 8 further comprising: capacitor means connected between said first and second transistor base leads.
Claim 15
Dependent Claim
25 words
A loop-seizing circuit according to claim 5 comprising an optical isolator serially connected with said second diode means for generating a reverse battery indication signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-04-23 | 1982-10-23 | 1983-04-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-04-23 | 1986-10-23 | 1987-04-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-04-23 | 1990-10-23 | 1991-04-24 | $7700.00 | Window Closed / Lapsed |