US3867567A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electronic data terminal interface
Assignee: AG Communication Systems Corp
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Filing: 1973-10-11
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Granted: 1975-02-18
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Expires: 1993-10-11
Abstract
Abstract An interface circuit for use between a data terminal and a data system for providing level shifting and isolation and having a receive channel that is powered by the same power supply as the transmit channel which is normally furnished with the data terminal.
Inventors
- 👤 Roger G Herron
- 👤 David B Freitag
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:59
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/20; H04L25/26
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
198 words
An electronic data terminal interface circuit connected between a data system and a data terminal, said data terminal including send driver means for recognizing data pulse signals in a code format, passive receive control means for providing mark and space pulse signals in a code format, and a dc power supply; said data system including send and receive signaling paths capable of recognizing and generating data pulses in a pulse train of code format; said electronic data terminal interface circuit comprising: send channel means for providing level shifting, ground isolation and noise rejection having an input connected to the send signaling path output of said data system and having an output connected to the series combination of the driver means and the dc power supply of said data terminal, and separate receive channel means providing level shifting, ground isolation and noise rejection having an input connected to the receive control means and having an output connected to the receive signaling path input of said data system, said send channel means including electronic power storage means for supplying said separate receive channel means, said electronic power storage means being charged from the dc power supply of said data terminal.
Claim 2
Dependent Claim
198 words
An electronic data terminal interface circuit connected between a data system and a data terminal, said data terminal including send driver means for recognizing data pulse signals in a code format, passive receive control means for providing mark and space pulse signals in a code format, and a dc power supply; said data system including send and receive signaling paths capable of recognizing and generating data pulses in a pulse train of code format; said electronic data terminal interface circuit comprising: send channel means for providing level shifting, ground isolation and noise rejection having an input connected to the send signaling path output of said data system and having an output connected to the series combination of the driver means and the dc power supply of said data terminal, and separate receive channel means providing level shifting, ground isolation and noise rejection having an input connected to the receive control means and having an output connected to the receive signaling path input of said data system, said send channel means including electronic power storage means for supplying said separate receive channel means, said electronic power storage means being charged from the dc power supply of said data terminal.
Claim 3
Dependent Claim
54 words
The interface circuit of claim 1 further characterized in that said receive channel means and said send channel means each include optical isolator means for providing noise rejection and ground isolation between the data system and the data terminal, said optical isolator means each including a light emitting element and a photo-sensitive control element.
Claim 4
Dependent Claim
47 words
The interface circuit of claim 2 further characterized in that said electronic power storage means includes a Zener diode and a capacitor operably connected to said receive channel means to limit the current and voltage storage characteristics so as to protect and supply said receive channel means.
Claim 5
Dependent Claim
47 words
An interface circuit as recited in claim 3 wherein said send channel means includes semiconductor means for limiting the output current to said data terminal, said send current limiting means being connected between said send channel optical isolator means and the output of said send channel means.
Claim 6
Dependent Claim
41 words
An interface circuit as recited in claim 4 wherein said send current limiting means includes semiconductor means for protecting against reverse polarity connection damage, said send channel reverse polarity protection means being connected at the output of said send channel means.
Claim 7
Dependent Claim
60 words
An interface circuit as recited in claim 3 wherein said receive channel means includes semiconductor means for limiting the input current to said interface circuit and through said passive receive control means of said data terminal, said receive current limiting means being connected between said receive channel opTical isolator means and said passive receive control means of said data terminal.
Claim 8
Dependent Claim
42 words
An interface circuit as recited in claim 6 wherein said receive current limiting means includes semiconductor means for protecting against reverse polarity connection damage, said receive channel reverse polarity protection means being connected to said receive control means of said data system.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-17 | 1978-08-19 | 1979-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-17 | 1982-08-19 | 1983-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-17 | 1986-08-19 | 1987-02-18 | $7700.00 | Window Closed / Lapsed |