Patent US4149069A successfully refreshed from Google Patents.
US4149069A
Expired / Lapsed
US
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Safety circuit for a data processing system producing binary signals
Assignee: Siemens AG
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Filing: 1977-09-19
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Granted: 1979-04-10
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Expires: 1997-09-19
Abstract
Abstract The invention relates to a safety circuit for a data processing system comprising two micro computers which operate in a redundant fashion receiving similar inputs and having similar output lines conveying coincident or corresponding signals during proper operation which are indirectly connected to a common push-pull amplifier. A transformer is connected in circuit with the push-pull amplifier and a conversion circuit constructed from the flip-flop trigger elements produces a pair of signals for operating the push-pull amplifier when the signal pair logic 1 exists. When the signal pair of logic 0 exists, the push-pull amplifier does not operate. The conversion circuit operates in connection with a clock pulse current supply for the two micro computers so that in the case of malfunction, no clock pulses are produced.
Inventors
- 👤 Horst Strelow
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 11:46
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1629; G06F11/1641; G05; G05B; G05B9/00; G05B9/02; G05B9/03; H; H03; H03K; H03K19/00; H03K19/003; H03K19/00392
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
328 words
A safety circuit for a clock actuated read-out from a data processing system wherein the safety circuit includes an amplifier means, an output transformer with its primary connected to the output of said amplifier, a rectifier connected to the secondary of said transformer, output means supplied from said rectifier wherein the improvement comprises a pair of micro computers (MR1, MR2) each having at least one data line (DL1, DL2) upon which similar binary signals from two micro computers (MR1, MR2) appear, a common pulse current supply (TG) connected to said micro computers, a pair of first pulse-edge triggered D-type flip-flops (K1, K10) respectively connected to receive on their D input terminals outputs of said micro computers and with their (Q) outputs connected to the reset inputs (R) of a second pair of pulse-edge triggered D-type flip-flops (K2, K20), and the input of said amplifier connected to the Q or Q outputs of one of said second pair of trigger circuit elements (K2, K20), synchronous clock pulses supplied from said pulse current supply (TG) to the C-inputs of said second pair of trigger circuit elements (K2, K20), the reset inputs (R) of said first pair trigger circuit elements (K1, K10) connected to an output of the pulse current supply (TG) which output delivers a reset signal (GL1, GL2, respectively), the D inputs of said second pair of flip-flops connected, respectively, to their Q outputs, a non-equivalent monitoring element (AD) which receives interrogation test pulses (TS) from said pulse current supply (TG), said monitoring element (AD) connected to the negated output Q of one of said second pair of trigger circuit elements (K2) and to the Q output of the other of said second pair of trigger circuit elements (K20), and said non-equivalent monitoring element (AD) producing output test pulses (TS) in the case of static as well as in the case of dynamic non-equivalent signals for the purpose of maintaining the pulse current supply (TG) in the on state.
Claim 2
Dependent Claim
328 words
A safety circuit for a clock actuated read-out from a data processing system wherein the safety circuit includes an amplifier means, an output transformer with its primary connected to the output of said amplifier, a rectifier connected to the secondary of said transformer, output means supplied from said rectifier wherein the improvement comprises a pair of micro computers (MR1, MR2) each having at least one data line (DL1, DL2) upon which similar binary signals from two micro computers (MR1, MR2) appear, a common pulse current supply (TG) connected to said micro computers, a pair of first pulse-edge triggered D-type flip-flops (K1, K10) respectively connected to receive on their D input terminals outputs of said micro computers and with their (Q) outputs connected to the reset inputs (R) of a second pair of pulse-edge triggered D-type flip-flops (K2, K20), and the input of said amplifier connected to the Q or Q outputs of one of said second pair of trigger circuit elements (K2, K20), synchronous clock pulses supplied from said pulse current supply (TG) to the C-inputs of said second pair of trigger circuit elements (K2, K20), the reset inputs (R) of said first pair trigger circuit elements (K1, K10) connected to an output of the pulse current supply (TG) which output delivers a reset signal (GL1, GL2, respectively), the D inputs of said second pair of flip-flops connected, respectively, to their Q outputs, a non-equivalent monitoring element (AD) which receives interrogation test pulses (TS) from said pulse current supply (TG), said monitoring element (AD) connected to the negated output Q of one of said second pair of trigger circuit elements (K2) and to the Q output of the other of said second pair of trigger circuit elements (K20), and said non-equivalent monitoring element (AD) producing output test pulses (TS) in the case of static as well as in the case of dynamic non-equivalent signals for the purpose of maintaining the pulse current supply (TG) in the on state.
Claim 3
Dependent Claim
75 words
A safety circuit according to claim 1 wherein said amplifier is a push-pull amplifier, including two amplifiers, an output transformer with its primary winding connected to said two amplifiers, one of said amplifiers (V1) connected to the negated (Q) output of said one of said second pair of trigger circuit elements (K2) and the second amplifier (V2) connected to the Q output of the other one of said second pair of trigger circuit elements (K20).
Claim 4
Dependent Claim
51 words
A safety circuit according to claim 2 wherein said first and second pairs of trigger circuit elements are D trigger circuit elements (K1, K10, K2, K20) and where one of the respective second pair of D trigger circuit elements (K2, K20) has its D input connected to its negated Q output.
Claim 5
Dependent Claim
46 words
A safety circuit according to claim 1 wherein said non-equivalent-monitoring element (AD) consists of an electronic switching amplifiers (TR), having a current supply and a rectifier circuit (D1, D2 D3, D4) which receives the signals to be monitored from said second pair of trigger circuit elements.
Claim 6
Dependent Claim
14 words
A safety circuit according to claim 4 wherein said switching amplifier is a transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-04-09 | 1982-10-09 | 1983-04-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-04-09 | 1986-10-09 | 1987-04-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-04-09 | 1990-10-09 | 1991-04-10 | $7700.00 | Window Closed / Lapsed |