MOS Interface circuit

Claim 1

An improved method of interfacing an MOS logic circuit utilizing an MOS output stage with a logic circuit having different signal requirements, the improvement comprising; coupling the output terminal of said MOS logic circuit to a first negative potential voltage source through a resistor with the polarity of said voltage source being selected and coupled across the MOS logic circuit such that said output stage operates as a source follower, coupling the output terminal of said MOS logic circuit to a first input terminal of a comparator, and coupling a second input terminal of said comparator to a reference voltage said reference voltage having a second negative potential and being of a magnitude between ground and said first negative potential to generate at an output terminal of said comparator a first signal compatible with the logic circuit with which said MOS logic circuit is to be interfaced, in response to a second signal on the output of said MOS logic circuit, said second signal having a first state having substantially a ground potential and a second state having a potential between said first and second negative potentials.