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US4144572A
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Accurate phase-measuring system using arithmetic synthesis
Assignee: RCA Corp
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Filing: 1977-08-15
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Granted: 1979-03-13
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Expires: 1997-08-15
Abstract
Abstract Circuit for comparing the difference in phase between two signals having like waveforms and adjusting the phase of one until the difference is zero. Two waveform generators, controlled by signals derived from the same clock source, produce the signals to be measured. One control signal is derived from the clock source by a fixed divider; the other, using an arithmetic synthesizer. The phase of the other control signal is adjusted by changing the frequency number of the arithmetic synthesizer and the phase difference is available as a binary number of n bits, where n is an integer. Precision of phase measurement in femtoseconds is possible.
Inventors
- 👤 Eugene R. Starner
- 👤 Edward J. Nossen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:00
CPC Classifications
G; G01; G01R; G01R25/00; G01R25/04
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
185 words
A circuit for measuring the phase difference between two signals comprising, in combination: clock source means for supplying first clock signals; arithmetic synthesizer means, responsive to said first clock signals, including frequency register means, adder means, and phase register means for producing binary output phase signals and overflow signals; means responsive to said first clock signals for producing second clock signals having a fixed relation to said first clock signals; first and second waveform generator means responsive to said overflow signals and said second clock signals, respectively, for producing signals having a given waveshape; correlator means responsive to the signal from said first waveform generator means and to a delayed signal from said second waveform generator means for producing a phase signal representing the phase difference between the signal from said first waveform generator means and said delayed signal from said second waveform generator means; and means for coupling said phase signal to the frequency register means and including means for modifying the contents of said frequency register to vary the phase of said overflow signal in a direction to produce a zero phase difference.
Claim 2
Dependent Claim
185 words
A circuit for measuring the phase difference between two signals comprising, in combination: clock source means for supplying first clock signals; arithmetic synthesizer means, responsive to said first clock signals, including frequency register means, adder means, and phase register means for producing binary output phase signals and overflow signals; means responsive to said first clock signals for producing second clock signals having a fixed relation to said first clock signals; first and second waveform generator means responsive to said overflow signals and said second clock signals, respectively, for producing signals having a given waveshape; correlator means responsive to the signal from said first waveform generator means and to a delayed signal from said second waveform generator means for producing a phase signal representing the phase difference between the signal from said first waveform generator means and said delayed signal from said second waveform generator means; and means for coupling said phase signal to the frequency register means and including means for modifying the contents of said frequency register to vary the phase of said overflow signal in a direction to produce a zero phase difference.
Claim 3
Dependent Claim
19 words
The invention as claimed in claim 1 wherein said means for producing second clock signals includes binary divider means.
Claim 4
Dependent Claim
24 words
The invention as claimed in claim 1 wherein said frequency register includes up/down counter means having control input means for determining the count direction.
Claim 5
Dependent Claim
91 words
The invention as claimed in claim 3 wherein said correlator means includes: comparator means responsive to the signal from said first waveform generator means and to a delayed signal from said second waveform generator means for producing first and second signals, representative of the direction of the phase difference between the signal from said first waveform generator means and the delayed signal from said second waveform generator means; and means for coupling said first and second signals from said comparator means to said control input means of said up/down counter means.
Claim 6
Dependent Claim
23 words
The invention as claimed in claim 4 including ramp generating means responsive to said binary output sum signals for producing the overflow signals.
Claim 7
Dependent Claim
135 words
In a circuit for controlling the phase of a signal including means for generating said signal in response to a control signal and clock source means for deriving clock signals having a given clock period, the improvement comprising; arithmetic synthesizer means responsive to said clock signals from said clock source means, including frequency register means for storing a frequency number and accumulator means for accumulating said frequency number into a phase number having a new value at the end of each clock period derived solely by adding said frequency number at the end of each clock period to the value of the phase number then already stored in said accumulator means, for producing signals representative of phase; and means for coupling said signal representative of phase to said means for generating as said control signal.
Claim 8
Dependent Claim
135 words
In a circuit for controlling the phase of a signal including means for generating said signal in response to a control signal and clock source means for deriving clock signals having a given clock period, the improvement comprising; arithmetic synthesizer means responsive to said clock signals from said clock source means, including frequency register means for storing a frequency number and accumulator means for accumulating said frequency number into a phase number having a new value at the end of each clock period derived solely by adding said frequency number at the end of each clock period to the value of the phase number then already stored in said accumulator means, for producing signals representative of phase; and means for coupling said signal representative of phase to said means for generating as said control signal.
Claim 9
Dependent Claim
21 words
The invention as claimed in claim 6 wherein said means for coupling includes ramp generator means for producing continuous phase signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-03-12 | 1982-09-11 | 1983-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-03-12 | 1986-09-11 | 1987-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-03-12 | 1990-09-11 | 1991-03-13 | $7700.00 | Window Closed / Lapsed |