Patent US4138615A successfully refreshed from Google Patents.
US4138615A
Expired / Lapsed
US
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Presettable integrating timing circuit
Assignee: United States Department of the Navy
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Filing: 1977-09-06
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Granted: 1979-02-06
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Expires: 1997-09-06
Abstract
Abstract A presettable integrating timing circuit is capable of comparing the timelt product of an input signal with a preset signal. Means, comprising an input and an output, integrate an electrical signal at the input into an integrated signal at the output. Means, having two inputs, one input being connected to the output of the integrating means, the other input being connectable to a reference voltage, are capable of comparing the magnitude of a signal appearing at the first-named input with the reference voltage. Means are connected to the integrating means for clamping the input of the integrating means at a desired value. A feedback circuit is connected between the output and the input of the integrating means, to prevent the integrating means from saturating.
Inventors
- 👤 James R. McKinlay
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:07
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/18; G06G7/184; G06G7/186; H; H03; H03K; H03K17/00; H03K17/28
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
179 words
A presettable integrating timer, capable of comparing the time-volt product of an input with a preset signal, comprising: means, comprising an input and an output, for integrating an electrical signal at the input into an integrated signal at the output, the means for integrating being an operational amplifier (op amp) integrator; means, having two inputs, one input being connected to the output of the integrating means, the other input being connectable to a reference voltage, the means being capable of comparing the magnitude of a signal appearing at the first named input with the reference voltage, the means for comparing comprising an operational amplifier (op amp) comparator; means, connected to the integrating means, for clamping the input of the integrating means at a desired value; and a feedback circuit, connected between the output and the input of the integrating means to prevent the integrating means from saturating, the feedback circuit comprising a series combination, connected between the output and the input of the operational amplifier integrator, comprising a resistor, a diode, an emitter follower, another diode, and another resistor.
Claim 2
Dependent Claim
179 words
A presettable integrating timer, capable of comparing the time-volt product of an input with a preset signal, comprising: means, comprising an input and an output, for integrating an electrical signal at the input into an integrated signal at the output, the means for integrating being an operational amplifier (op amp) integrator; means, having two inputs, one input being connected to the output of the integrating means, the other input being connectable to a reference voltage, the means being capable of comparing the magnitude of a signal appearing at the first named input with the reference voltage, the means for comparing comprising an operational amplifier (op amp) comparator; means, connected to the integrating means, for clamping the input of the integrating means at a desired value; and a feedback circuit, connected between the output and the input of the integrating means to prevent the integrating means from saturating, the feedback circuit comprising a series combination, connected between the output and the input of the operational amplifier integrator, comprising a resistor, a diode, an emitter follower, another diode, and another resistor.
Claim 3
Dependent Claim
29 words
The timer according to claim 1, further comprising: means, whose input is connected to the output of the operational amplifier comparator, for increasing the power output of the comparator.
Claim 4
Dependent Claim
19 words
The timer according to claim 2, wherein: the means for increasing the power output is a Darlington emitter follower.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-02-05 | 1982-08-07 | 1983-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-02-05 | 1986-08-07 | 1987-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-02-05 | 1990-08-07 | 1991-02-06 | $7700.00 | Window Closed / Lapsed |