Selective enhancement of phosphorus diffusion by implanting halogen ions

Claim 1

In a method of making a bipolar monolithic integrated circuit that includes the steps of diffusing boron and then phosphorus into at least two discrete areas of an N-type silicon surface to form a discrete bipolar electrical component at each area, the improvement which comprises, selectively enhancing phosphorus diffusion in one of said areas by implanting halogen ions into said one area before boron diffusion effective to produce a deeper phosphorus diffusion in said one area than said other area without also enhancing the boron diffusion, whereby a closer spacing between boron and phosphorus diffusion fronts is obtained in said one area than said other area.

Claim 5

A method of using one boron diffusion and one phosphorus diffusion to simultaneously make both high gain and low gan bipolar transistors in a monolithic integrated circuit, said method comprising: providing an N-type silicon surface having a first discrete area where a higher gain transistor is to be formed and a second discrete area where a lower gain transistor is to be formed; implanting halogen ions in only the first of said areas in a dosage of at least 1 × 10 15 halogen ions per square centimeter, effective to accelerate phosphorus diffusion in said first area but not said second area; providing an identical surface concentration source of boron for diffusion into both said first and second areas; diffusing said boron simultaneously into both areas to form transistor base regions thereat of substantially similar depth below said silicon surface; providing an identical surface concentration source of phosphorus for diffusion into both areas; and diffusing said phosphorus simultaneously into both of said base regions to form transistor emitter regions therein, with the emitter region in said first area having a depth greater than the emitter region in the second area, resulting in a narrower base width and higher gain transistor in said first area than in said second area.

Claim 6

A method of using one boron diffusion and one phosphorus diffusion to simultaneously make both high gain and low gan bipolar transistors in a monolithic integrated circuit, said method comprising: providing an N-type silicon surface having a first discrete area where a higher gain transistor is to be formed and a second discrete area where a lower gain transistor is to be formed; implanting halogen ions in only the first of said areas in a dosage of at least 1 × 10 15 halogen ions per square centimeter, effective to accelerate phosphorus diffusion in said first area but not said second area; providing an identical surface concentration source of boron for diffusion into both said first and second areas; diffusing said boron simultaneously into both areas to form transistor base regions thereat of substantially similar depth below said silicon surface; providing an identical surface concentration source of phosphorus for diffusion into both areas; and diffusing said phosphorus simultaneously into both of said base regions to form transistor emitter regions therein, with the emitter region in said first area having a depth greater than the emitter region in the second area, resulting in a narrower base width and higher gain transistor in said first area than in said second area.

Claim 7

A method of making bipolar transistors with mutually different gain characteristics in a monolithic integrated circuit comprising the steps of: identically depositing boron by ion implantation onto a plurality of discrete areas of an N-type silicon surface where bipolar transistors are to be formed; masking a first plurality of said areas to isolate them from a halogen ion beam; irradiating an unmasked second plurality of said areas with a halogen ion-containing beam in a dosage of at least 1 × 10 15 ions per square centimeter effective to enhance phosphorus diffusion at said second plurality of areas, said halogen being a member selected from the group consisting of fluorine, chlorine and bromine, said irradiation implanting said halogen ions to a depth below said surface about as deep as boron ions enter said surface in said boron deposition; diffusing the deposition boron simultaneously into said first and second areas to form transistor base regions of generally similar depths beneath said silicon surface; identically depositing phosphorus onto said silicon surface within said first and second plurality of areas for providing bipolar transistor emitter regions within said base regions; and diffusing said phosphorus into said surface to form deeper emitter regions in said first plurality of areas than in said second plurality of areas, whereby bipolar transistors of narrower base width and higher gain are formed in said first plurality of areas than in said second plurality of areas.

Claim 8

A method of making bipolar transistors with mutually different gain characteristics in a monolithic integrated circuit comprising the steps of: identically depositing boron by ion implantation onto a plurality of discrete areas of an N-type silicon surface where bipolar transistors are to be formed; masking a first plurality of said areas to isolate them from a halogen ion beam; irradiating an unmasked second plurality of said areas with a halogen ion-containing beam in a dosage of at least 1 × 10 15 ions per square centimeter effective to enhance phosphorus diffusion at said second plurality of areas, said halogen being a member selected from the group consisting of fluorine, chlorine and bromine, said irradiation implanting said halogen ions to a depth below said surface about as deep as boron ions enter said surface in said boron deposition; diffusing the deposition boron simultaneously into said first and second areas to form transistor base regions of generally similar depths beneath said silicon surface; identically depositing phosphorus onto said silicon surface within said first and second plurality of areas for providing bipolar transistor emitter regions within said base regions; and diffusing said phosphorus into said surface to form deeper emitter regions in said first plurality of areas than in said second plurality of areas, whereby bipolar transistors of narrower base width and higher gain are formed in said first plurality of areas than in said second plurality of areas.