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US4133611A
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Two-page interweaved random access memory configuration
Assignee: Xerox Corp
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Filing: 1977-07-08
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Granted: 1979-01-09
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Expires: 1997-07-08
Abstract
Abstract A random access memory (RAM) containing 256 memory cells organized as two pages, each page containing 16 8-bit wide working registers. RAM row address circuitry as well as read-write and page-select circuitry are provided. A fixed transistor static RAM cell is used as the memory cell. Double rail transfer of data is employed. The memory cells and bit lines associated with each of the two pages is interweaved in the array so that the precharged circuitry and the RAM input/output circuitry associated with each of the pages is alternately configured on the chip. TABLE OF CONTENTS Subject Background of the Invention Summary of the Invention Brief Description of the Drawings Detailed Description of the Preferred Embodiment The System Block Diagram Microprocessor Unit Pin Designations Clock and Timing Signals System Timing The ROM The Stack Area The RAM Area Elimination of Race Conditions in the RAM The ALU and Control Time Slot End Predictor Precharged Data Line Driver
Inventors
- 👤 Lamar T. Baker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:44
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018557; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/413; G11C11/417; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09441; H03K19/09443; Y; Y10; Y10S; Y10S257/00; Y10S257/923
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
153 words
A memory on a semiconductor chip comprising: (a) a plurality of memory cells each having a bit sense terminal, said memory cells arranged in a plurality of rows and a plurality of columns wherein each column has a first and a last memory cell; (b) a plurality of bit sense lines, each one being associated with a particular column by being coupled to the bit sense terminals of the memory cells in said particular column; (c) means coupled to said bit sense terminal of the first memory cell in said particular column for precharging the associated bit sense line; (d) means coupled to the bit sense terminal of the last memory cell in said particular column for reading data from and writing data into said memory cells in said particular column; and (e) said particular columns arranged such that a first row comprises alternate first and last memory cells associated with particular columns.
Claim 2
Dependent Claim
153 words
A memory on a semiconductor chip comprising: (a) a plurality of memory cells each having a bit sense terminal, said memory cells arranged in a plurality of rows and a plurality of columns wherein each column has a first and a last memory cell; (b) a plurality of bit sense lines, each one being associated with a particular column by being coupled to the bit sense terminals of the memory cells in said particular column; (c) means coupled to said bit sense terminal of the first memory cell in said particular column for precharging the associated bit sense line; (d) means coupled to the bit sense terminal of the last memory cell in said particular column for reading data from and writing data into said memory cells in said particular column; and (e) said particular columns arranged such that a first row comprises alternate first and last memory cells associated with particular columns.
Claim 3
Dependent Claim
72 words
The memory of claim 1 wherein: (a) a bit sense line is positioned on said chip so as to be adjacent to the memory cells in a particular column; (b) said precharging means is positioned on said chip adjacent a first memory cell and in line with said particular column; and (c) said read-write means is positioned on said chip adjacent a last memory cell and in line with said particular column.
Claim 4
Dependent Claim
48 words
The memory of claim 2 further comprising: a word select terminal as part of a memory cell; and a plurality of word select lines, each one being associated with a particular row by being coupled to the word select terminals of the memory cells in said particular row.
Claim 5
Dependent Claim
17 words
The memory of claim 3 further comprising: row select circuitry for selectively activating said word select lines.
Claim 6
Dependent Claim
76 words
The memory of claim 4 wherein said columns having first memory cells in said first row provide a first plurality of bits defining a first page; said columns having last memory cells in said first row provide a second plurality of bits defining a second page; and wherein there is further provided means for activating said read-write means such that data is read from or written into a selected one of said first and second pages.
Claim 7
Dependent Claim
36 words
The memory of claim 3 wherein said memory cell further comprises means responsive to a signal on a word select line for connecting or isolating said memory cell from said first and second bit sense lines.
Claim 8
Dependent Claim
21 words
The memory of claim 6 wherein said memory cell further comprises a memory storage element in circuit with said connecting means.
Claim 9
Dependent Claim
14 words
The memory of claim 7 wherein said memory storage element is a bistable flip-flop.
Claim 10
Dependent Claim
199 words
A random access memory on a semiconductor chip comprising: (a) a plurality of memory cells each having first and second bit sense terminals, said memory cells arranged on said chip in a plurality of rows and a plurality of columns wherein each column has a first and a last memory cell; (b) a plurality of first bit sense lines, each one being associated with a particular column by being coupled to the first bit sense terminal of the memory cells in said particulr column; (c) a plurality of second bit sense lines, each one being associated with a particular column by being coupled to the second bit sense terminal of the memory cells in said particular column; (d) means coupled to the first and second bit sense terminals in said particular column for precharging the associated bit sense lines; (e) means coupled to the first and second bit sense terminals of the last memory cell in said particular column for reading data from and writing data into said memory cells in said particular column; and (f) said particular columns arranged on said chip such that a first row comprises alternate first and last memory cells associated with particular columns.
Claim 11
Dependent Claim
199 words
A random access memory on a semiconductor chip comprising: (a) a plurality of memory cells each having first and second bit sense terminals, said memory cells arranged on said chip in a plurality of rows and a plurality of columns wherein each column has a first and a last memory cell; (b) a plurality of first bit sense lines, each one being associated with a particular column by being coupled to the first bit sense terminal of the memory cells in said particulr column; (c) a plurality of second bit sense lines, each one being associated with a particular column by being coupled to the second bit sense terminal of the memory cells in said particular column; (d) means coupled to the first and second bit sense terminals in said particular column for precharging the associated bit sense lines; (e) means coupled to the first and second bit sense terminals of the last memory cell in said particular column for reading data from and writing data into said memory cells in said particular column; and (f) said particular columns arranged on said chip such that a first row comprises alternate first and last memory cells associated with particular columns.
Claim 12
Dependent Claim
79 words
The memory of claim 9 wherein: said first and second bit sense lines are positioned on said chip so as to be adjacent to the memory cells in a particular column thus forming first and second column lines; said precharging means is positioned on said chip adjacent a first memory cell and in line with said particular column; and said read-write means is positioned on said chip adjacent a last memory cell and in line with said particular column.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-01-08 | 1982-07-10 | 1983-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-01-08 | 1986-07-10 | 1987-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-01-08 | 1990-07-10 | 1991-01-09 | $7700.00 | Window Closed / Lapsed |