Device for the digital multiplexing of quasi-synchronous trains

Claim 1

A device for multiplexing n quasi-synchronous digital trains, called incoming trains Ti, having the same nominal rate Fe and with real rates Fei (1≦i≦n) into an outgoing multiplex train with a nominal rate Fs slightly faster than n times the nominal rate of each incoming train, the outgoing train being arranged in successive frames each comprising, at defined locations, a given identification character CI, at least one n-bit justification indication IJ and a possible justification J having at the most one bit per incident train, the device comprising n channel units and one multiplexing unit: the multiplexing unit comprising a time base generating a signal at the frequency Fs of the bits of the outgoing train, a signal HL at the frequency Fs/n and having holes at the locations corresponding to the identification character CI and to each justification indication in each frame, this signal HL being transmitted by a first connection of the multiplexing unit to each channel unit; and each channel unit intended to generate a synchronized train T'i supplying the multiplexing unit via a second connection, and comprising a memorizing assembly for the incoming train, controlled for writing by the clock signal of this train, those frequency is Fei and for reading by a reading signal HL 1 deduced from the signal HL which is supplied by the multiplexing unit, to deliver a resulting train T"i, a phase comparator between the signal Fei and HL 1 , a request circuit for possible justifications controlled by the comparator and an inhibition circuit generating the signal HL 1 from the signal HL when there is a justification request, wherein the multiplexing unit also supplies each channel unit, via a third connection, with a signal SJ constituted by a clock pulse of Fs/n corresponding to each justification indication IJ, the pulse corresponding to the last justification IJ of each frame being maintained until the identification character CI of the following frame and wherein each channel unit also comprises a circuit for the restitution of the frame frequency from the signals SJ and HL, a circuit for controlling the inhibition circuit from the signal at the frame frequency, from the signal SJ and from the justification request signal, a circuit for copying the resulting train T"i delivered by the memorization and restitution assembly for the train T'i, controlled by the signal HL and associated with a circuit for inserting the value of each justification indication IJ at the location provided under the control of the signal SJ and of the output signal of the justification request circuit.

Claim 2

A device for multiplexing n quasi-synchronous digital trains, called incoming trains Ti, having the same nominal rate Fe and with real rates Fei (1≦i≦n) into an outgoing multiplex train with a nominal rate Fs slightly faster than n times the nominal rate of each incoming train, the outgoing train being arranged in successive frames each comprising, at defined locations, a given identification character CI, at least one n-bit justification indication IJ and a possible justification J having at the most one bit per incident train, the device comprising n channel units and one multiplexing unit: the multiplexing unit comprising a time base generating a signal at the frequency Fs of the bits of the outgoing train, a signal HL at the frequency Fs/n and having holes at the locations corresponding to the identification character CI and to each justification indication in each frame, this signal HL being transmitted by a first connection of the multiplexing unit to each channel unit; and each channel unit intended to generate a synchronized train T'i supplying the multiplexing unit via a second connection, and comprising a memorizing assembly for the incoming train, controlled for writing by the clock signal of this train, those frequency is Fei and for reading by a reading signal HL 1 deduced from the signal HL which is supplied by the multiplexing unit, to deliver a resulting train T"i, a phase comparator between the signal Fei and HL 1 , a request circuit for possible justifications controlled by the comparator and an inhibition circuit generating the signal HL 1 from the signal HL when there is a justification request, wherein the multiplexing unit also supplies each channel unit, via a third connection, with a signal SJ constituted by a clock pulse of Fs/n corresponding to each justification indication IJ, the pulse corresponding to the last justification IJ of each frame being maintained until the identification character CI of the following frame and wherein each channel unit also comprises a circuit for the restitution of the frame frequency from the signals SJ and HL, a circuit for controlling the inhibition circuit from the signal at the frame frequency, from the signal SJ and from the justification request signal, a circuit for copying the resulting train T"i delivered by the memorization and restitution assembly for the train T'i, controlled by the signal HL and associated with a circuit for inserting the value of each justification indication IJ at the location provided under the control of the signal SJ and of the output signal of the justification request circuit.