Expandable memory for asynchronous PCM multiplexer

Claim 1

In a telecommunication system with a transmitting terminal at an input end of a PCM link, a receiving terminal at an output end of said link, a number z of incoming lines at said transmitting terminal carrying respective streams of message bits organized in lower-order frames divided into a multiplicity of time slots occurring at a first bit cadence, multiplexing means at said transmitting terminal for the bit-by-bit interleaving of said lower-order frames from said incoming lines into a higher-order frame sent out via said link to said receiving terminal at z times a second bit cadence higher than said first bit cadence to provide additional time slots for the inclusion of ancillary bits constituting supervisory signals, a set of first expandable memories respectively inserted between said incoming lines and said multiplexing means for facilitating the introduction of said ancillary bits into said additional time slots, a number z of outgoing lines at said receiving terminal respectively paired with said incoming lines, demultiplexing means at said receiving terminal for redistributing the interleaved message bits of said higher-order frame to said outgoing lines, and a set of second expandable memories respectively inserted between said demultiplexing means and said outgoing lines for facilitating the suppression of ancillary bits introduced at said first expandable memories, the improvement wherein each expandable memory of said first set comprises: register means with n stages for the temporary storage of n consecutive message bits of an incoming bit stream; writing-control means for timing the recurrent sequential loading of said stages at a rate corresponding to said first bit cadence; reading-control means for timing the recurrent sequential unloading of said stages, during intervals of predetermined length representing several subframes of a recurrent higher-order frame, at a rate corresponding to said second bit cadence but with an initial gap at the beginning of each subframe for the insertion of at least one ancillary bit; comparison means connected to said writing-control means and to said reading-control means for determining the delay between the loading and the unloading of a given stage of said register means and for generating a preparatory signal upon said delay falling short of a predetermined period equaling less than n bit cycles of said first bit cadence; timing means for generating distinctive control pulses in different subframes, said comparison means including circuitry controlled by said timing means for emitting a stuffing command in response to the generation of said preparatory signal in an early subframe of said higher-order frame; blocking means responsive to said stuffing command and to a control pulse from said timing means for inhibiting the unloading of a stage of said register means in a predetermined time slot of a later subframe of said higher-order frame, following said early subframe, normally allocated to a message bit; and insertion means responsive to said stuffing command and to a control pulse from said timing means for generating, in at least one initial gap of a subframe following said early subframe, a discriminating bit informing the corresponding memory of said second set of the absence of a message bit in said predetermined time slot.