Patent US4131907A successfully refreshed from Google Patents.
US4131907A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Short-channel V-groove complementary MOS device
Assignee: UNIVERSAL SEMICONDUCTOR Inc A CORP OF CA
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Filing: 1977-09-28
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Granted: 1978-12-26
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Expires: 1997-09-28
Abstract
Abstract An improved short-channel complementary MOS transistor structure is provided. The problems of low punch-through voltage breakdown, and "short-channel effects" are particularly addressed and solved. Accurate and precise field protection of all area surrounding the channel, source and drain regions of both the p-channel MOS transistor device and the n-channel transistor device is simply and effectively accomplished. The threshold voltage of the n-channel MOS transistor device is precisely controlled by a boron implantation. The method of manufacturing such device is disclosed.
Inventors
- 👤 Paul H. Ouyang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:45
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0195; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/858; Y; Y10; Y10S; Y10S148/00; Y10S148/07; Y10S148/168
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
350 words
A complementary metal-oxide-semiconductor field effect device comprising: a lightly N-doped semiconductor substrate having a first surface and a lightly P-doped tub therein; a first P-type region lying beneath and extending to said first surface in said semiconductor substrate; a second P-type region lying beneath and extending to said first surface in said semiconductor substrate; a first V-groove extending from said first surface into said semiconductor substrate lying between said first and said second P-type regions, said first V-groove having two side surfaces and two end surfaces exposing said first P-type region with a first side surface and exposing said second P-type region with a second side surface; a first relatively thin insulating layer overlying said first V-groove; a first N-type layer lying beneath and extending to said first surface in said substrate surrounding said first P-type region, said second P-type region and said first V-groove; a first N-type region lying beneath and extending to said first surface in said N-doped tub; a second N-type region lying beneath and extending to said first surface in said N-doped tub; a second V-groove extending from said first surface into said P-doped tub disposed between said first and said second N-type regions having two side surfaces and two end surfaces; a first P-type layer lying beneath and adjacent to a portion of said first and said second N-type regions exposed by all four surfaces of said V-groove; a second P-type layer lying beneath and extending to said first surface in said N-type tub surrounding said first and said second N-type regions and said second V-groove; a second relatively thin insulating layer overlying said second V-groove; a relatively thick insulating layer of substantially uniform thickness disposed over said first surface of said semiconductor substrate having openings therein over said first and said second P-type regions, and said first and said second N-type regions; first, second, third, and fourth electrodes respectively making electrical contact with said first, and said second P-type regions and said first and said second N-type regions; and fifth and sixth electrodes respectively overlying said first and said second relatively thin insulating layers.
Claim 2
Dependent Claim
350 words
A complementary metal-oxide-semiconductor field effect device comprising: a lightly N-doped semiconductor substrate having a first surface and a lightly P-doped tub therein; a first P-type region lying beneath and extending to said first surface in said semiconductor substrate; a second P-type region lying beneath and extending to said first surface in said semiconductor substrate; a first V-groove extending from said first surface into said semiconductor substrate lying between said first and said second P-type regions, said first V-groove having two side surfaces and two end surfaces exposing said first P-type region with a first side surface and exposing said second P-type region with a second side surface; a first relatively thin insulating layer overlying said first V-groove; a first N-type layer lying beneath and extending to said first surface in said substrate surrounding said first P-type region, said second P-type region and said first V-groove; a first N-type region lying beneath and extending to said first surface in said N-doped tub; a second N-type region lying beneath and extending to said first surface in said N-doped tub; a second V-groove extending from said first surface into said P-doped tub disposed between said first and said second N-type regions having two side surfaces and two end surfaces; a first P-type layer lying beneath and adjacent to a portion of said first and said second N-type regions exposed by all four surfaces of said V-groove; a second P-type layer lying beneath and extending to said first surface in said N-type tub surrounding said first and said second N-type regions and said second V-groove; a second relatively thin insulating layer overlying said second V-groove; a relatively thick insulating layer of substantially uniform thickness disposed over said first surface of said semiconductor substrate having openings therein over said first and said second P-type regions, and said first and said second N-type regions; first, second, third, and fourth electrodes respectively making electrical contact with said first, and said second P-type regions and said first and said second N-type regions; and fifth and sixth electrodes respectively overlying said first and said second relatively thin insulating layers.
Claim 3
Dependent Claim
11 words
The device of claim 1 wherein electrodes are made of aluminum.
Claim 4
Dependent Claim
24 words
The device of claim 1 wherein said first and said second N-type regions are exposed by the opposite side surfaces of said second V-groove.
Claim 5
Dependent Claim
26 words
The device of claim 1 wherein the impurity concentration of said N-doped semiconductor substrate ranges from about 10 13 to about 10 15 atoms/cm 3 .
Claim 6
Dependent Claim
25 words
The device of claim 1 wherein the impurity concentration of said P-doped tub ranges from about 10 14 to about 5×10 15 atoms/cm 3 .
Claim 7
Dependent Claim
25 words
The device of claim 1 wherein the impurity concentration of said first P-type layer ranges from about 5×10 15 to 10 18 atoms/cm 3 .
Claim 8
Dependent Claim
19 words
The device of claim 1 wherein the thickness of said first p-type layer ranges from 0.05 to 1 micron.
Claim 9
Dependent Claim
18 words
The device of claim 1 wherein said first P-type region and said first semiconductor substrate are electrically connected.
Claim 10
Dependent Claim
18 words
The device of claim 1 wherein said second P-type region and said first N-type region are electrically connected.
Claim 11
Dependent Claim
17 words
The device of claim 1 wherein said P-doped tub and said second N-type region are electrically connected.
Claim 12
Dependent Claim
379 words
A complementary metal-oxide-semiconductor field effect device comprising: a. a lightly P-doped semiconductor substrate having a first surface and a lightly N-doped tub therein, b. a first P-type region lying beneath and extending to said first surface in said N-doped tub, c. a second P-type region lying beneath and extending to said first surface in said N-doped tub, d. a first V-groove extending from said first surface into said N-doped tub lying between said first and said second P-type regions, said first V-groove having two side surfaces and two end surfaces exposing said first P-type region with a first side surface and exposing said second P-type region with a second side surface, e. a first N-type layer lying beneath and extending to said first surface in said N-doped tub surrounding said first P-type region, said second P-type region, said first V-groove and said N-doped tub, f. a first relatively thin insulating layer overlying said first V-groove, g. a first electrode overlying said first relatively thin insulating layer, h. a first N-type region lying beneath and extending to said first surface in said semiconductor substrate, i. a second N-type region lying beneath and extending to said first surface in said semiconductor substrate, j. a second V-groove extending from said first surface into said semiconductor substrate disposed between said first and said second N-type regions, k. a first P-type layer lying beneath and adjacent to a portion of said first and said second N-type region in said semiconductor substrate exposed by all four surfaces of said second V-groove, l. a second P-type layer lying beneath and extending to said first surface in said semiconductor substrate surrounding said first and said second N-type regions and said second V-groove, m. a second relatively thin insulating layer overlying said second V-groove, n. a second electrode overlying said second relatively thin insulating layer, o. a relatively thick insulating layer of substantially uniform thickness disposed over said first surface of said semiconductor substrate having openings therein over said first and said second P-type regions, and said first and said second N-type regions, and p. first, second, third and fourth electrodes ov overlying said relatively thick insulating layer respectively making electrical contact with said first and said second P-type regions, and said first and said second N-type regions.
Claim 13
Dependent Claim
379 words
A complementary metal-oxide-semiconductor field effect device comprising: a. a lightly P-doped semiconductor substrate having a first surface and a lightly N-doped tub therein, b. a first P-type region lying beneath and extending to said first surface in said N-doped tub, c. a second P-type region lying beneath and extending to said first surface in said N-doped tub, d. a first V-groove extending from said first surface into said N-doped tub lying between said first and said second P-type regions, said first V-groove having two side surfaces and two end surfaces exposing said first P-type region with a first side surface and exposing said second P-type region with a second side surface, e. a first N-type layer lying beneath and extending to said first surface in said N-doped tub surrounding said first P-type region, said second P-type region, said first V-groove and said N-doped tub, f. a first relatively thin insulating layer overlying said first V-groove, g. a first electrode overlying said first relatively thin insulating layer, h. a first N-type region lying beneath and extending to said first surface in said semiconductor substrate, i. a second N-type region lying beneath and extending to said first surface in said semiconductor substrate, j. a second V-groove extending from said first surface into said semiconductor substrate disposed between said first and said second N-type regions, k. a first P-type layer lying beneath and adjacent to a portion of said first and said second N-type region in said semiconductor substrate exposed by all four surfaces of said second V-groove, l. a second P-type layer lying beneath and extending to said first surface in said semiconductor substrate surrounding said first and said second N-type regions and said second V-groove, m. a second relatively thin insulating layer overlying said second V-groove, n. a second electrode overlying said second relatively thin insulating layer, o. a relatively thick insulating layer of substantially uniform thickness disposed over said first surface of said semiconductor substrate having openings therein over said first and said second P-type regions, and said first and said second N-type regions, and p. first, second, third and fourth electrodes ov overlying said relatively thick insulating layer respectively making electrical contact with said first and said second P-type regions, and said first and said second N-type regions.
References Cited (Backward Citations)
US3975752A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-12-25 | 1982-06-26 | 1982-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-12-25 | 1986-06-26 | 1986-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-12-25 | 1990-06-26 | 1990-12-26 | $7700.00 | Window Closed / Lapsed |