Independently controllable multiple address registers for a data processor

Claim 1

In a digital date processor having an addressable storage unit including an address bus and having a number of registers coupled to a common bus for transfer of data to and from said common bus, said processor being capable of producing command signals evoking the execution of different instructions, the combination comprising: a storage control unit coupled to said common bus and responsive to one of said command signals for receiving a control word from said common bus, and for producing therefrom a plurality of control signals including first and second enable signals and mutually independent first and second address-modification signals; first and second address registers coupled to said common bus and capable of being independently incremented and decremented by said first and second address-modification signals, respectively; and gating means for selectively coupling said first and second address registers to said address bus of said addressable storage unit in response to said first and second enable signals, respectively.