US4128881A — Shared memory access control system for a multipr…

Claim 1

Independent Claim 267 words

In a multiprocessor system having a plurality of processors, each of which has a normal operational state and certain special condition operational states, said system including a common memory unit and said plurality of processors; a shared memory unit access control system comprising: a fixed address supply source, one in each processor, for generating address information of multiple bits and for addressing and accessing said common memory unit in accordance therewith, said address information generated by each said fixed address supply source in each of said respective processors being identical, and a sequential state indicate signal generator, one in each processor, for producing an output signal of a single bit which selectively assumes logic "1" or "0" values in accordance with a predetermined sequence when one of said certain special condition operational states exists; and said system further comprising: fixing means external to at least each of said processors except for one and responsive to said output signal for fixing at least one bit of said multiple bits, provided by said fixed address supply source of said at least each of said processors except for one, to the logic "1" or "0" values of the output signal produced by said sequential state indicate signal generator, said at least one bit of each respective one of said at least each of said processors except for one being respectively different in identity in relation to said multiple bits, whereby to uniquely alter said address information produced by said fixed address supply source of said at least each of said processors except for one during said special condition operational states.

Claim 2

Dependent Claim 267 words

In a multiprocessor system having a plurality of processors, each of which has a normal operational state and certain special condition operational states, said system including a common memory unit and said plurality of processors; a shared memory unit access control system comprising: a fixed address supply source, one in each processor, for generating address information of multiple bits and for addressing and accessing said common memory unit in accordance therewith, said address information generated by each said fixed address supply source in each of said respective processors being identical, and a sequential state indicate signal generator, one in each processor, for producing an output signal of a single bit which selectively assumes logic "1" or "0" values in accordance with a predetermined sequence when one of said certain special condition operational states exists; and said system further comprising: fixing means external to at least each of said processors except for one and responsive to said output signal for fixing at least one bit of said multiple bits, provided by said fixed address supply source of said at least each of said processors except for one, to the logic "1" or "0" values of the output signal produced by said sequential state indicate signal generator, said at least one bit of each respective one of said at least each of said processors except for one being respectively different in identity in relation to said multiple bits, whereby to uniquely alter said address information produced by said fixed address supply source of said at least each of said processors except for one during said special condition operational states.

Claim 3

Dependent Claim 40 words

In a multiprocessor system according to claim 1, wherein said processors are each formed in the same pattern with LSI chips so that said fixed address supply source of each processor is constructed to produce the same fixed address information.

Claim 4

Dependent Claim 99 words

In a multiprocessor system according to claim 1, wherein said sequential state indicate signal generator for producing said output signal which selectively assumes the logic "1" or "0" values in said special condition operational state comprises: a sequence flip-flop for producing an interrupt sequence signal and an LPSW execution sequence signal, means for obtaining the logical sum of said interrupt sequence signal and said LPSW execution sequence signal, means for providing an address information output indicate signal, and means for synchronizing said logical sum with said address information output indicate signal, whereby to produce said sequential state indicate signal.

Claim 5

Dependent Claim 101 words

In a multiprocessor system according to claim 1, wherein said system includes common bus lines carrying signals from each of the processors to the common memory unit, and wherein each said fixing means external to a respective one of said at least each of said processors except for one comprises means for connecting the output of the sequential state indicate signal generator of said respective one of said at least each of said processors except for one to a respective bus line which is different for each said respective one of said at least each of said processors except for one.

Claim 6

Dependent Claim 233 words

In a multiprocessing system which includes a plurality of central processing units arranged to access a common memory and to operate in accordance with at least one special condition operational state, each central processing unit including a fixed address supply means for supplying a multi-bit address signal representing a fixed address in said common memory to be accessed by said central processing unit, said central processing units being of identical internal construction so that said multi-bit address signal of any given central processing unit is identical to the corresponding multi-bit address signal of each and every other central processing unit; the improvement wherein each respective central processing unit is provided with respective generating means for generating internally in said processing unit a single-bit output, signal in accordance with said at least one special condition operational state; and said system being provided with fixing means, one for at least each respective central processing unit except for one, external to said at least each respective central processing unit except for one and responsive to said single-bit output signal thereof for modifying a respective bit of at least each said multi-bit address signal except for one in a given manner which is unique for each of said at least each respective central processing unit except for one, whereby each of said central processing units accesses a different one of said fixed addresses in said common memory.

Claim 7

Dependent Claim 233 words

In a multiprocessing system which includes a plurality of central processing units arranged to access a common memory and to operate in accordance with at least one special condition operational state, each central processing unit including a fixed address supply means for supplying a multi-bit address signal representing a fixed address in said common memory to be accessed by said central processing unit, said central processing units being of identical internal construction so that said multi-bit address signal of any given central processing unit is identical to the corresponding multi-bit address signal of each and every other central processing unit; the improvement wherein each respective central processing unit is provided with respective generating means for generating internally in said processing unit a single-bit output, signal in accordance with said at least one special condition operational state; and said system being provided with fixing means, one for at least each respective central processing unit except for one, external to said at least each respective central processing unit except for one and responsive to said single-bit output signal thereof for modifying a respective bit of at least each said multi-bit address signal except for one in a given manner which is unique for each of said at least each respective central processing unit except for one, whereby each of said central processing units accesses a different one of said fixed addresses in said common memory.

Claim 8

Dependent Claim 128 words

In the system of claim 5, wherein each said respective generating means includes: sequential state indicating means for producing at least one state signal indicating a sequential state of said respective central processing unit; and logic means connected to said sequential state indicating means and responsive to said at least one state signal for producing said single-bit output signal; each said fixing means comprising applying means connecting said logic means to said respective bit of said multi-bit address signal from said fixed address supply means for applying said single-bit output signal to said respective bit, the identity of said respective bit being unique for each multi-bit signal of each fixed address supply means, whereby to produce a unique address signal for each of said fixed address supply means.

Claim 9

Dependent Claim 45 words

In the system of claim 6, wherein said logic means is responsive to input signals including an address information output indicate signal, whereby said address signal is uniquely modified in synchronization with the supply of said fixed address signal by said fixed address supply means.

Claim 10

Dependent Claim 35 words

In the system of claim 6 including bus means between each of said central processing units and said common memory for carrying said uniquely modified address signal from each of said fixed address supply means.

Claim 11

Dependent Claim 31 words

In the system of claim 8, wherein said bus means includes a plurality of bus lines, one for each central processing unit, each carrying one of said uniquely modified address signals.

Claim 12

Dependent Claim 95 words

In the system of claim 5, each central processing unit including means for providing an address information output indicate signal and a data information output indicate signal, wherein at least each fixed address supply means except for one is responsive to said address information output indicate signal and to said data information output indicate signal for synchronizing the modification of at least each said multi-bit address signal except for one representing a fixed address with the supply of said fixed address signal by said fixed address supply means and with said data information output signal.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1981-12-04	1982-06-05	1982-12-05	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1985-12-04	1986-06-05	1986-12-05	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1989-12-04	1990-06-05	1990-12-05	$7700.00	Window Closed / Lapsed

Shared memory access control system for a multiprocessor system

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