Data processing system having status indicating and storage means

Claim 2

A data processing system comprising addressable bulk storage means; processing means; means for coupling the processing means to the bulk storage means; the processing means comprising a plurality of processing subsystems having conflicting contentions for use of addresses of the bulk storage means; communication control means; means for coupling the communication control means to the processing means; the communication control means comprising memory means for storing a plurality of addresses and, associated with each address, a first status indicium indicating whether the address is in use and a second status indicium indicating whether the address was contended for by a subsystem while the address was in use, and address reporting means for providing to the processing means an address which is stored in association with a second status indicium indicating that the address was contended for while in use and a first status indicium indicating that the address is not presently in use.

Claim 3

A data processing sytem comprising: a plurality of data processing subsystems; bulk storage means having addressable storage locations; means for coupling each of the data processing subsystems to said bulk storage means; the data processing subsystems using and contending for the use of addressable storage locations in the bulk storage means; a communication control unit separate from the bulk storage means and processing subsystems; means for coupling the data processing subsystems to said communication control unit; said communication control unit comprising memory means for storing addresses for said bulk storage means and associated with each address, separate status indicia concerning the addresses, means responsive to a contention for access by one of said processing subsystems to a storage location for selectively updating the content of said memory means including means for storing in the memory means status indicia associated with the contended for address which indicates whether the associated address is in use or not in use and means for storing status indicia in the memory means which indicates whether a processing subsystem contended for such address while the address was indicated to be in use, means for inspecting the content of said memory means and for selecting an address stored in the memory means and having status indicia indicating such address is no longer in use but indicating such address was contended for while previously in use, and means for providing the selected address to the coupling means.

Claim 4

A data processing sytem comprising: a plurality of data processing subsystems; bulk storage means having addressable storage locations; means for coupling each of the data processing subsystems to said bulk storage means; the data processing subsystems using and contending for the use of addressable storage locations in the bulk storage means; a communication control unit separate from the bulk storage means and processing subsystems; means for coupling the data processing subsystems to said communication control unit; said communication control unit comprising memory means for storing addresses for said bulk storage means and associated with each address, separate status indicia concerning the addresses, means responsive to a contention for access by one of said processing subsystems to a storage location for selectively updating the content of said memory means including means for storing in the memory means status indicia associated with the contended for address which indicates whether the associated address is in use or not in use and means for storing status indicia in the memory means which indicates whether a processing subsystem contended for such address while the address was indicated to be in use, means for inspecting the content of said memory means and for selecting an address stored in the memory means and having status indicia indicating such address is no longer in use but indicating such address was contended for while previously in use, and means for providing the selected address to the coupling means.

Claim 5

A system according to claim 2 wherein said processing subsystems are characterized by providing an address of a desired storage location when contending for use thereof; said means for updating comprising means for comparing an address provided by a processing subsystem against the addresses contained in said memory means for an equality therebetween, means responsive to said status indicia for providing a first signal for a storage location which is indicated to be in use and a second signal for a storage location which is indicated not to be in use, and means responsive to an equality and said second signal for storing status indicia in the memory means in association with the address being compared which indicates a storage lOcation in use.

Claim 6

A system according to claim 3 wherein said means for updating comprises means responsive to said equality and said first signal for storing status indicia in the memory means in association with the address being compared which indicates a storage location has been contended for while in use.

Claim 7

A system according to claim 3 wherein said means for updating comprises means for indicating when all addresses in said memory means have been compared without finding an equality and means responsive to the last named indication for storing the address being compared into said memory means in association with status indicia indicating that the corresponding storage location is in use.

Claim 8

A system according to claim 2 wherein the means for inspecting comprises means which when initiated is operable for sequentially scanning through each of said stored addresses and means for monitoring the status indicia associated with each scanned address and detecting those which indicate the associated address is no longer in use but were previously contented for while in use.

Claim 9

The system according to claim 2 wherein the status indicia for each address comprises status indicia indicating which one of said processing subsystems contended for such address when it was already in use, and further comprising means for identifying which of the processing subsystems is contending for use, said updating means comprising means responsive to the processing subsystem identifying means for updating the stored status indicia associated with a contended for address to indicate which processing subsystem contended for such address.

Claim 10

The system according to claim 7 wherein the address providing means includes gating means responsive to the identifying means for enabling a detected address to be provided to the coupling means only when the indicia of such detected address indicates that it was previously contended for by the presently identified processing subsystem.

Claim 11

The system according to claim 2 wherein the processing subsystems are characterized in that each begins use of a storage location in the bulk storage means by reading information therefrom and by ending use by writing information therein, and further characterized in that each processing subsystem provides the contended for address to the communication control means when contending for such address; the system comprising means for providing a first control signal indicating that a processing subsystem has ended its use of a provided address and for providing a second control signal indicating that information has been successfully written therein; the updating means comprising a register for temporarily storing the provided address, means responsive to the first control signal for locating in the memory means the status indicia associated with an address equal to that stored in said register means, said storing means being operative in response to said second control signal for storing status indicia indicating a non-use condition in association with the located address after information has been successfully written into the bulk storage location for the provided address.

Claim 12

Apparatus for indicating the status of storage locations in an addressable memory which storage locations are shared by a plurality of control means, the control means providing signals when requesting access to the addressable memory, the signals including the address of the storage location to which access is requested and a command signal indicating whether the request is to begin or is to end use of such storage location, the apparatus comprising: an input circuit for receiving said signals from said control means; an output circuit for providing signals back to the control means; memory means for storing addresses for said addressable memory means and associated with each address is stored status indicia indicating whether the storage location specified by the address is in use or is not in use and also indicatiNg whether a control means contended for the storage location while it was in use; means responsive to said received signals for updating the stored status indicia and comprising means for locating in the memory means the received address and its associated status indicia and means responsive to a received command signal for setting the located status indicia to indicate the storage location for the associated address is either in use or is not in use depending on whether the command indicates an access is to begin or is to end, respectively; means for selectively inspecting the status indicia in said memory means and for locating an address associated with status indicia which status indicia indicates that the storage location for the associated address is no longer in use but was contended for while previously in use; and means responsive to such detection for providing the associated address at the output circuit.

Claim 13

Apparatus for indicating the status of storage locations in an addressable memory which storage locations are shared by a plurality of control means, the control means providing signals when requesting access to the addressable memory, the signals including the address of the storage location to which access is requested and a command signal indicating whether the request is to begin or is to end use of such storage location, the apparatus comprising: an input circuit for receiving said signals from said control means; an output circuit for providing signals back to the control means; memory means for storing addresses for said addressable memory means and associated with each address is stored status indicia indicating whether the storage location specified by the address is in use or is not in use and also indicatiNg whether a control means contended for the storage location while it was in use; means responsive to said received signals for updating the stored status indicia and comprising means for locating in the memory means the received address and its associated status indicia and means responsive to a received command signal for setting the located status indicia to indicate the storage location for the associated address is either in use or is not in use depending on whether the command indicates an access is to begin or is to end, respectively; means for selectively inspecting the status indicia in said memory means and for locating an address associated with status indicia which status indicia indicates that the storage location for the associated address is no longer in use but was contended for while previously in use; and means responsive to such detection for providing the associated address at the output circuit.

Claim 14

Apparatus according to claim 10 additionally comprising read means operable for sequentially reading out from the memory means the stored addresses and associated status indicia, wherein the means for inspecting and locating comprises address register means for storing a received address, means for comparing the address stored in said register means with each read out address for a predetermined relationship therebetween and means for causing the read means to read out the stored addresses and associated indicia until the compare means detects said predetermined relationship, and wherein the means for inspecting and locating comprises means for causing the read means to continue reading addresses after said predetermined relationship is detected until stored status indicia for each address in said memory means has been inspected.

Claim 15

A data processing system comprising: a plurality of data processing subsystems; bulk storage means having addressable storage locations; means for coupling each of the processing subsystems to said bulk storage means; the data processing subsystems using and contending for the use of addressable storage locations in the bulk storage means and providing an address of a desired storage location and a command indicating whether to begin or to end use of the address; a communication control unit; means for coupling the communication control unit to said processing subsystems; said communication control unit comprising memory means having a plurality of memory locations, each for storing a bulk storage means address and associated first and second status indicia, the first status indicium indicating whether the storage location identified by the associated address is presently in use and the second status indicium indicating whether the storage location was contended for while indicated to be in use, updating means comprising means for comparing a provided address with each of the addresses stored in said memory means for detecting an equality therebetween, means responsive to the compare means for indicating a lack of equality between the provided address and all of said addresses stored in the memory means, means for monitoring the status indicia associated with each stored address being compared, controllable means for modifying the first and second status indicia associated with each address being compared and control means responsive to one of said begin use commands and the detection of an equality between the address provided with such command and a stored address for controlling the controllable status indicia modifying means thereby causing such associated first status indicium to be modified to indicate an in use status if it presently indicates a non-use status and thereby causing such associated second status indicium to be modified to indicate a contended for status if the first status indicium indicates a presently in use condition, the control means including means responsive to said indication of a lack of equality for storing the address provided with the command into A memory location along with first status indicia which indicates an in use status, means for inspecting the content of said memory means and for detecting an address having first status indicium indicating a non-use condition and second status indicium indicating a contended for condition while previously in use and means responsive to the last mentioned detection for providing a signal back to the coupling means indicating an address is no longer in use that has been contended for.

Claim 16

A data processing system comprising: a plurality of data processing subsystems; bulk storage means having addressable storage locations; means for coupling each of the processing subsystems to said bulk storage means; the data processing subsystems using and contending for the use of addressable storage locations in the bulk storage means and providing an address of a desired storage location and a command indicating whether to begin or to end use of the address; a communication control unit; means for coupling the communication control unit to said processing subsystems; said communication control unit comprising memory means having a plurality of memory locations, each for storing a bulk storage means address and associated first and second status indicia, the first status indicium indicating whether the storage location identified by the associated address is presently in use and the second status indicium indicating whether the storage location was contended for while indicated to be in use, updating means comprising means for comparing a provided address with each of the addresses stored in said memory means for detecting an equality therebetween, means responsive to the compare means for indicating a lack of equality between the provided address and all of said addresses stored in the memory means, means for monitoring the status indicia associated with each stored address being compared, controllable means for modifying the first and second status indicia associated with each address being compared and control means responsive to one of said begin use commands and the detection of an equality between the address provided with such command and a stored address for controlling the controllable status indicia modifying means thereby causing such associated first status indicium to be modified to indicate an in use status if it presently indicates a non-use status and thereby causing such associated second status indicium to be modified to indicate a contended for status if the first status indicium indicates a presently in use condition, the control means including means responsive to said indication of a lack of equality for storing the address provided with the command into A memory location along with first status indicia which indicates an in use status, means for inspecting the content of said memory means and for detecting an address having first status indicium indicating a non-use condition and second status indicium indicating a contended for condition while previously in use and means responsive to the last mentioned detection for providing a signal back to the coupling means indicating an address is no longer in use that has been contended for.

Claim 17

A system according to claim 12 wherein the control means further comprises means responsive to an end use command for causing the modifying means to modify the first status indicium associated with the detected address to indicate a non-use condition.

Claim 18

A system according to claim 12 wherein the last mentioned means comprises means for providing the detected address to the coupling means.

Claim 19

A data processing system comprising: a plurality of data processing subsystems; bulk storage means having addressable storage locations each identified by an address; means for coupling each of the data processing subsystems to said storage means the data processing subsystems using and contending for the use of addresses in the bulk storage means; a communication control unit separate from the bulk storage means and processing subsystems; means for coupling the data processing subsystems to said communication control unit; said communication control unit comprising memory means for storing addresses for said bulk storage means and associated with each address separate status indicia concerning such address, means responsive to a contention for access by one of said processing subsystems to an address for selectively updating the content of said memory means including means for storing in the memory means status indicia in association with the contended for address which indicates whether the associated address is in use or not in use and means for storing status indicia which indicates whether each one of the processing subsystems contended for such address while the address was indicated to be in use, means for forming a signal identifying a particular processing subsystem which is contending for use, means responsive to said signal for locating in said memory means an address having status indicia indicating such address is no longer in use and which also indicates such address was contended for by the particular data processing subsystem which is identified by said signal while such address was previously in use and means for providing the located address to the coupling means.

Claim 20

A data processing system comprising: a plurality of data processing subsystems; bulk storage means having addressable storage locations each identified by an address; means for coupling each of the data processing subsystems to said storage means the data processing subsystems using and contending for the use of addresses in the bulk storage means; a communication control unit separate from the bulk storage means and processing subsystems; means for coupling the data processing subsystems to said communication control unit; said communication control unit comprising memory means for storing addresses for said bulk storage means and associated with each address separate status indicia concerning such address, means responsive to a contention for access by one of said processing subsystems to an address for selectively updating the content of said memory means including means for storing in the memory means status indicia in association with the contended for address which indicates whether the associated address is in use or not in use and means for storing status indicia which indicates whether each one of the processing subsystems contended for such address while the address was indicated to be in use, means for forming a signal identifying a particular processing subsystem which is contending for use, means responsive to said signal for locating in said memory means an address having status indicia indicating such address is no longer in use and which also indicates such address was contended for by the particular data processing subsystem which is identified by said signal while such address was previously in use and means for providing the located address to the coupling means.

Claim 21

A system according to claim 15 wherein the memory means comprises addressable memory locations, and the updating means comprises means for locating an address for updating which includes a counter for counting through a series of states for identifying memory locations and means for detecting equality between addresses stored in the identified memory locations and the address being contended for.

Claim 22

A system according to claim 16 wherein the means for locating an address to be provided to the coupling means comprises a register for storing a state of the counter, and gating means responsive to the stored status indicia for storing into the register the state of the counter thereby identifying a memory location storing an address associated with status indicia which indicates such address is no longer in use but was contended for by the identified data processing subsystem.

Claim 23

Status indicating and storage apparatus for the addresses of a storage means, the apparatus comprising memory means having a plurality of memory locations each for storing an address and associated therewith signal indicia comprising a first signal indicium indicating whether the associated address is in use and a second signal indicium indicating any one of a plurality of initiating means waiting to initiate an access to the associated address of such storage means, register means for sToring an address, register means for storing an operator indicating that an address is to be marked in use or not in use, means responsive to the stored operator for comparing the address in said address storing register with the addresses stored in said memory means and upon detecting equality selectively storing a signal indicium in association with the detected address in said memory means thereby marking such address in use or not in use in accordance with the stored operator, and means providing a unique output signal to an initiating means in response to any selected signal indicia whenever the second signal indicium indicates an initiating means is writing to initiate an access and the first signal indicium indicates the associated address is not in use.

Claim 24

Status indicating and storage apparatus for the addresses of a storage means, the apparatus comprising memory means having a plurality of memory locations each for storing an address and associated therewith signal indicia comprising a first signal indicium indicating whether the associated address is in use and a second signal indicium indicating any one of a plurality of initiating means waiting to initiate an access to the associated address of such storage means, register means for sToring an address, register means for storing an operator indicating that an address is to be marked in use or not in use, means responsive to the stored operator for comparing the address in said address storing register with the addresses stored in said memory means and upon detecting equality selectively storing a signal indicium in association with the detected address in said memory means thereby marking such address in use or not in use in accordance with the stored operator, and means providing a unique output signal to an initiating means in response to any selected signal indicia whenever the second signal indicium indicates an initiating means is writing to initiate an access and the first signal indicium indicates the associated address is not in use.

Claim 25

Status indicating and storage means according to claim 18 comprising a counter for sequentially counting through a plurality of states corresponding to the memory locations in said memory means and means for causing the content of the memory locations corresponding to the states of said counter to be read out for comparison.

Claim 26

Status indicating and storage apparatus according to claim 19 wherein memory locations may be effectively empty in that any addresses stored therein are neither in use nor awaiting use, means monitoring the memory locations as they are read out and for detecting an effectively empty one, a further register means, means for storing in the further register means the state of the counter corresponding to an effectively empty memory location, means for providing an output signal upon completing a count through all locations in said memory means, means responsive to said output signal for setting the state of the counter back to the state corresponding to that stored in said further register means and means for storing the address stored in the address register means into the memory location corresponding to the set state of the counter together with a signal indicium determined by the operator.

Claim 27

Status indicating and storage means according to claim 20 wherein the monitoring means detects all effectively empty memory locations and the means for storing the state of the counter includes means for overwriting in said further register means the previous stored state of the counter with a new state as each subsequent effectively empty memory location is detected, the address storing means thereby storing into the last effectively empty memory location detected before said output signal.

Claim 28

Status indicating and storage means for multiple means which access a common addressable memory means comprising a memory having multiple memory locations each for storing an address for said common memory and associated with each address storing an indication of whether such address is in use and an indication for each of said multiple means of whether each is waiting for access to the associated address when not in use, means for scanning said memory locations and for causing the contents to be read out one by one, means for designating one of said multiple means and means for monitoring the readout from said memory for an address which has associated indications identifying that the multiple means identified by said designating means is waiting for access to the associated address and indicating that such address is not in use, and means responsive to the monitoring of such an address and being further responsive to the designating means for providing a predetermined signal to the multiple means identified by said designating means.

Claim 29

Status indicating and storage means for multiple means which access a common addressable memory means comprising a memory having multiple memory locations each for storing an address for said common memory and associated with each address storing an indication of whether such address is in use and an indication for each of said multiple means of whether each is waiting for access to the associated address when not in use, means for scanning said memory locations and for causing the contents to be read out one by one, means for designating one of said multiple means and means for monitoring the readout from said memory for an address which has associated indications identifying that the multiple means identified by said designating means is waiting for access to the associated address and indicating that such address is not in use, and means responsive to the monitoring of such an address and being further responsive to the designating means for providing a predetermined signal to the multiple means identified by said designating means.

Claim 30

Status indicating the storage means according to claim 22 including a temporary storage means, and means responsive to said monitoring means for selectively storing a signal in the temporary storage means corresponding to a memory means storage location having a stored address with associated indications designating that such address is not in use and that the multiple means designated by said designating means is waiting for access to such address, and means for Selectively resetting the scanning means back to the memory storage location which corresponds to the signal contained in said temporary storing means.

Claim 31

Status indicating and storage means according to claim 23 wherein said means for selectively storing is operative for storing a signal corresponding to only one storage location at any one time and includes means for overwriting a previously stored signal as the memory is scanned.

Claim 32

Status indicating and storage means according to claim 22 including means for selectively coupling an address back to the multiple means which is indicated by the designating means.

Claim 33

Apparatus for indicating the status of addresses of addressable memory means, which comprises control means for providing memory addresses and control signals and for initiating accesses to the addressable memory means at the provided memory addresses; a control memory for storing memory addresses each together with an associated indicia comprising a status indicium indicating whether the control means is waiting to access at the associated address and a use indicium indicating whether the associated address is in use; means for updating the control memory including means for receiving a provided address and an associated control signal directing such address to be marked in use or marked not in use, means for storing the received control signal, address register means for storing the received address, means for comparing the address stored in the address register means with the individual addresses in the control memory and for detecting an address equal to the received address, and means responsive to the stored control signal and a detected equality for changing the indicia associated with the detected address in accordance with the stored control signal; and means for selectively inspecting the stored indicia and for providing an output indication to the control means indicating that a particular address provided by the control means is not in use and that the control means is waiting to initiate an access therein.

Claim 34

Apparatus for indicating the status of addresses of addressable memory means, which comprises control means for providing memory addresses and control signals and for initiating accesses to the addressable memory means at the provided memory addresses; a control memory for storing memory addresses each together with an associated indicia comprising a status indicium indicating whether the control means is waiting to access at the associated address and a use indicium indicating whether the associated address is in use; means for updating the control memory including means for receiving a provided address and an associated control signal directing such address to be marked in use or marked not in use, means for storing the received control signal, address register means for storing the received address, means for comparing the address stored in the address register means with the individual addresses in the control memory and for detecting an address equal to the received address, and means responsive to the stored control signal and a detected equality for changing the indicia associated with the detected address in accordance with the stored control signal; and means for selectively inspecting the stored indicia and for providing an output indication to the control means indicating that a particular address provided by the control means is not in use and that the control means is waiting to initiate an access therein.