Semiconductor device

Claim 2

A semiconductor device comprising a semiconductor body having a surface and comprising a substantially homogeneously doped semiconductor layer disposed at said surface, at least a bipolar transistor located in said body and comprising an emitter zone of a first conductivity type adjoining said surface, a base zone of second conductivity type which adjoins said surface and within said body surrounds said emitter zone entirely, and a collector zone that is of said first conductivity type and adjoins said surface, said base zone comprising an active base region and base contact region, said base contact region being associated with said active base region and being deeper and more highly doped than said active base region, said emitter zone being located substantially completely within said active base region, said base contact region and said emitter zone being contacted at said surface for electrical connection, said collector zone comprising a surface-adjoining collector contact region of said first conductivity type which is contacted at said surface and has a higher doping concentration than the adjoining semiconductor material, said active base region, when viewed in a direction parallel to said surface, being present between said base contact region and said collector contact region, said doped semiconductor surface layer surrounding said collector contact region and said base regions, whereby said emitter zone, active base region, base contact region and collector contact region are provided in and have a different doping concentration than said doped semiconductor surface layer.

Claim 3

A semiconductor device as in claim 1, wherein the width of said active base region, measured in the direction from the base contact region to the collector contact region, is at most equal to the smallest distance between said active base region and said collector contact region.

Claim 4

A semiconductor device as in claim 2, wherein said width is at most equal to half said distance.

Claim 5

A semiconductor device as in claim 1, wherein said doped semiconductor surface layer is of said second conductivity type.

Claim 6

A semiconductor device as in claim 1, wherein the smallest distance from said collector contact region to said active base region is sufficiently small so that the depletion zone of the junction between said collector and base regions extends over the whose part of said doped semiconductor surface layer intermediate thereto.

Claim 7

A semiconductor device as in claim 1, wherein said base contact region is connected through said doped semiconductor surface layer to a buried second conductivity type layer and forms therewith a coherent region of said second conductivity type, said body comprising a substrate having a conductivity type opposite that of said layer, said buried layer being present between said doped semiconductor surface layer and said substrate and extendind to below said collector contact region.

Claim 8

A semiconductor device as in claim 1, wherein said doped semiconductor surface layer comprises part of said transistor and part of a second bipolar transistor which is complementary to said first transistor, said second transistor comprising a surface-adjoining emitter zone of the same conductivity type as said semiconductor layer and a likewise surface-adjoining base zone of a conductivity type opposite to that of said doped semiconductor surface layer, said base zone surrounding said emitter zone entirely within said body, said second transistor comprising a collector zone formed by said doped semiconductor surface layer.

Claim 9

A semiconductor device as in claim 1, wherein said doped semiconductor surface layer is of n type conductivity.

Claim 10

A method of manufacturing a semiconductor device as recited in claim 1, comprising the steps of providing a semiconductor body comprising a substantially homogeneously doped semiconductor layer, providing first and second masking layers successively one on the other on the surface of said layer, which masking layers can be etched selectively relative to each other, providing a first aperture in said second masking layer at the area where the base contact region is to be provided and a second aperture in said second masking layer at the area where the collector contact region is to be provided, providing at said first masking layer located within said second aperture a mask to prevent etching thereof, removing by etching the exposed part of said first masking layer located within said first aperture, then introducing a second conductivity type dopant via said first aperture into said semiconductor layer to form at least a part of the base contact region and then covering the thus produced base contact region with an electrically insulating layer, subjecting at least the edge portion of the masking layers located within said first aperture and nearest to said second aperture to an etchant which attacks only one of the two said masking layers so that said one masking layer is etched away selectively over a lateral distance which is smaller than half of the shortest distance between said first and second apertures, the thus etched said masking layer being masked on its upper side against said etching process by a mask extending thereon up to the edge of said first aperture, and then providing the active base region at the surface part of said semiconductor layer present below said etched-away portion by introducing therein a second conductivity type dopant and forming said emitter zone and said collector contact region by the introducing therein a first conductivity type dopant via said second aperture.

Claim 11

A method as in claim 9, wherein said lateral distance is less than one-third said shortest distance between said first and second apertures.

Claim 12

A method as in claim 9, wherein the masking layer that is etched away selectively laterally is the first masking layer and the mask present thereon and extending up to the edge of the first aperture is formed by said second masking layer.

Claim 13

A method as in claim 9, wherein the masking layer which is etched away selectively laterally is the second masking layer.

Claim 14

A method as in claim 9, wherein said first masking layer consists of silicon-nitride and said second masking layer consists of silicon oxide.