Abstract A charge-coupled analogue delay line has a plurality of analogue storage locations, and a gating means, which may include charge-coupled shift register, for enabling input to and output from each of the storage locations in turn. The storage locations are formed on a semiconducting substrate and each has a diffused zener diode to act as a source of minority carriers and a priming electrode for drawing off and holding a charge of minority carriers from the zener diode. A sample-holding electrode, upon receipt of a gating signal by a gating electrode, receives from the priming electrode and holds a charge of minority carriers of magnitude indicative of the magnitude of the signal to be stored. An output electrode is arranged to transfer the charge held by the sample-holding electrode to a diffused output channel. Since signal samples in this delay line are transferred just once into a storage location and then out again they suffer less from degradation due to residual charges then is the case in conventional CCD delay lines in which samples are passed from location to location.
A charge-coupled delay line comprising: a signal input line; a signal output line; a plurality of analogue storage locations connected in parallel to said input and output lines, and gating means for enabling output from each of said locations in turn in a predetermined sequence to said signal output line and for enabling input to each of said locations in turn in said predetermined sequence from said signal input line, wherein each of said storage locations is a charge-coupled device formed on a doped semi-conducting substrate and including: a stepped priming electrode; a zener diode formed in said substrate and arranged to inject minority carriers into said substrate under said priming electrode; a stepped sample-holding electrode; a gate electrode between and adjacent to a charge-output edge of said priming electrode and a charge-input edge of said sample-holding electrode; an output electrode having a charge-input edge adjacent to a charge-output edge of said sample-holding electrode; and an output channel formed in the said substrate and extending under said output electrode for capturing minority-carrier charges.
Claim 2
Dependent Claim
173 words
A charge-coupled delay line comprising: a signal input line; a signal output line; a plurality of analogue storage locations connected in parallel to said input and output lines, and gating means for enabling output from each of said locations in turn in a predetermined sequence to said signal output line and for enabling input to each of said locations in turn in said predetermined sequence from said signal input line, wherein each of said storage locations is a charge-coupled device formed on a doped semi-conducting substrate and including: a stepped priming electrode; a zener diode formed in said substrate and arranged to inject minority carriers into said substrate under said priming electrode; a stepped sample-holding electrode; a gate electrode between and adjacent to a charge-output edge of said priming electrode and a charge-input edge of said sample-holding electrode; an output electrode having a charge-input edge adjacent to a charge-output edge of said sample-holding electrode; and an output channel formed in the said substrate and extending under said output electrode for capturing minority-carrier charges.
Claim 3
Dependent Claim
25 words
The delay line of claim 1, wherein said output channels of said storage locations are connected to said signal-output connection via a common sample-and-hold circuit.
Claim 4
Dependent Claim
23 words
The delay line of claim 1, including clearing means for re-setting said output channels of said storage location to a fixed reset voltage.