Low power random access memory with self-refreshing cells

Claim 2

A memory device comprising: capacitive storage means for storing electrical charge; input control means for selectively providing an electrical path to said capacitive storage means; a first switching means having a control line and a pair of terminals; a second switching means having a control line and a pair of terminals, one terminal of each of said first and second switching means coupled to said capacitive storage means, said control line of said second switching means coupled to the other terminal of said first switching means; a variable capacitance means for providing capacitance, the amount of said capacitance having a predetermined relationship to the voltage across said capacitance means, and capacitance means coupled between the other terminal of said second switching means and said control line of said second switching means; whereby, by the application of a varying signal to said variable capacitance means, the state of charge in said capacitive storage means is refreshed.

Claim 3

The memory device defined by claim 1 wherein said variable capacitance means comprises a depletion mode, field-effect transistor having a gate and a pair of terminals, said gate of said depletion mode transistor coupled to said control line of said second switching means and one terminal of said depletion mode transistor coupled to said other terminal of said second switching means.

Claim 4

The memory device defined by claim 2 wherein said first and second switching means each comprise a field-effect transducer and wherein said control lines comprise gates of said field-effect transistors.

Claim 5

The memory device defined by claim 3 wherein said capacitive storage means comprises a second depletion mode, field-effect transistor having a gate and a pair of terminals, said gate of said second depletion mode transistor coupled to said gate of said first switching means.

Claim 6

The memory device defined by claim 4 wherein said first switching means is a depletion mode transistor with a threshold voltage closer to zero volts than the threshold voltage of said second depletion mode transistor.

Claim 7

The memory device defined by claim 5 wherein said transistors are all n-channel devices employing polycrystalline silicon gates.

Claim 8

In a semiconductor memory device having a storage capacitor for storing electrical charge and an electrical network for refreshing said charge where said electrical network includes a first and a second transistor, each of which having a control electrode and a pair of terminals, one terminal of each of said transistors coupled to one terminal of the said storage capacitor, another terminal of said storage capacitor coupled to said control electrode of said first transistor, and said control electrode of said second transistor coupled to the other terminal of said first transistor, an improvement comprising: a variable capacitor coupled between the other terminals of said first and second transistors, said variable capacitor for providing a larger capacitance when said first transistor is in a non-conductive state and a smaller capacitance when said first transistor is in a conductive state; whereby, by the application of varying signals to said variable capacitor, the charge on said storage capacitor is refreshed.

Claim 9

In a semiconductor memory device having a storage capacitor for storing electrical charge and an electrical network for refreshing said charge where said electrical network includes a first and a second transistor, each of which having a control electrode and a pair of terminals, one terminal of each of said transistors coupled to one terminal of the said storage capacitor, another terminal of said storage capacitor coupled to said control electrode of said first transistor, and said control electrode of said second transistor coupled to the other terminal of said first transistor, an improvement comprising: a variable capacitor coupled between the other terminals of said first and second transistors, said variable capacitor for providing a larger capacitance when said first transistor is in a non-conductive state and a smaller capacitance when said first transistor is in a conductive state; whereby, by the application of varying signals to said variable capacitor, the charge on said storage capacitor is refreshed.

Claim 10

The memory device defined by claim 7 wherein said variable capacitor comprises a depletion mode, field-effect transistor.

Claim 11

The memory device defined by claim 8 wherein said varying signal is coupled to one terminal of said depletion mode transistor.

Claim 12

The memory device defined by claim 9 wherein the other terminal of said depletion mode transistor is coupled to said other terminal of said second transistor, and the gate of said depletion mode transistor is coupled to said other terminal of said first transistor.

Claim 13

The memory device defined by claim 10 wherein said depletion mode transistor and said first and second transistors are n-channel devices.

Claim 14

A low power MOS buffer having an input terminal comprising: a first and a second field-effect transistor, each having a gate and a pair of terminals; a capacitor coupled between one of said terminals of said first and second transistors; a source of current coupled to said one terminal of said first transistors; delay means for providing a time delay coupled between said input terminal and said gate of said second transistor; gating means for providing a gated signal coupled to said delay means, said input terminal and said gate of said first transistor; whereby no current is drawn by said first and second transistors except during a transition by said buffer from one state to another state.

Claim 15

A low power MOS buffer having an input terminal comprising: a first and a second field-effect transistor, each having a gate and a pair of terminals; a capacitor coupled between one of said terminals of said first and second transistors; a source of current coupled to said one terminal of said first transistors; delay means for providing a time delay coupled between said input terminal and said gate of said second transistor; gating means for providing a gated signal coupled to said delay means, said input terminal and said gate of said first transistor; whereby no current is drawn by said first and second transistors except during a transition by said buffer from one state to another state.

Claim 16

The buffer defined by claim 12 wherein an inverter is coupled to said input terminal and wherein said inverter provides said delay.

Claim 17

The buffer defined by claim 13 wherein said gating means comprises a logic gate.

Claim 18

The buffer defined by claim 12 wherein said source of current comprises a depletion mode transistor.

Claim 19

The buffer defined by claim 15 wherein said capacitor comprises a depletion mode device.