Malfunction detection system for a microprocessor based programmable controller

Claim 2

In a programmable controller having a controller processor which connects to a plurality of separate I/O interface racks through an I/O address bus and an I/O data bus, the improvement therein comprising: means at each of said I/O interface racks for detecting a malfunction condition thereat and generating a fault indicating logic signal when such a malfunction condition is detected; a logic gate at each of said I/O interface racks having one input connected to receive said fault indicating logic signal, a second input and an output; an I/O fault line which connects in daisy chain fashion between said I/O interface racks and to said controller processor, said I/O fault line connecting the output of the logic gate in each of said I/O interface racks with the second input of the logic gate in the next I/O interface rack in the daisy chain and connecting the output of the logic gate in the last I/O interface rack in the daisy chain to the controller processor; and means at said controller processor for receiving said fault indicating logic signal on said I/O fault line and indicating the presence of a malfunction.

Claim 3

The improvement as recited in claim 1 in which said means at said controller processor includes means for inhibiting the controller processor from executing programmable controller instructions when said fault indicating logic signal is present on said I/O fault line.

Claim 4

The improvement as recited in claim 1 in which said means at said controller processor includes timing means which is enabled when said fault indicating logic signal is present on said I/O fault line and which generates a reset signal at an output thereon when said fault indicating logic signal is present for a preselected time interval, and an I/O reset line connects to the output of said timing means and to each of said I/O interface racks to couple said reset signal thereto.

Claim 5

The improvement as recited in claim 3 in which watchdog timer means at said controller processor is coupled to said I/O reset line and is coupled to monitor the occurrence of a periodic event within said controller processor, said watchdog timer means being operable to generate a reset signal on said I/O reset line when said monitored periodic event does not occur within a preselected time interval.

Claim 6

The improvement as recited in claim 4 in which said controller processor includes: a microprocessor which executes instructions stored in a memory; a Boolean processor which is responsive to control signals from said microprocessor to perform logical operations on data stored within said memory; and a set of instructions stored in said memory which are periodically executed by said microprocessor and which direct the Boolean processor to execute a prescribed sequence of operations, which compare the actual state of said Boolean processor with a predetermined state after the execution of the prescribed sequence of operations and which inhibit the occurrence of said monitored event when the actual state of said Boolean processor is not the same as said predetermined state.

Claim 7

A programmable controller comprising: a memory which stores instructions; a microprocessor connected to said memory, said microprocessor being operable to read instructions out of said memory and execute them; a Boolean processor coupled to said memory and said microprocessor, said Boolean processor being operable in response to control signals from said microprocessor to perform logical operations on data stored within said memory; malfunction indicating means which includes a watchdog timer coupled to said microprocessor to detect the occurrence of a preselected periodic event, said malfunction indicating means being operable to indicate a malfunction when said preselected periodic event does not occur within a preselected time period as determined by the timing out of said watchdog timer; and wherein the instructions stored in said memory include a set of instructions which are periodically executed by said microprocessor while said programmable controller is on line to test the operation of said Boolean processor, said set of instructions including: a first subset of instructions which direct the Boolean processor to execute a prescribed sequence of operations; a second subset of instructions which compare the actual state of said Boolean processor with a predetermined state after the execution of said first subset; and a third subset of instructions which enable said indicating means when the actual state of said Boolean processor is not the same as said predetermined state by inhibiting the occurrence of said preselected periodic event.

Claim 8

A programmable controller comprising: a memory which stores instructions; a microprocessor connected to said memory, said microprocessor being operable to read instructions out of said memory and execute them; a Boolean processor coupled to said memory and said microprocessor, said Boolean processor being operable in response to control signals from said microprocessor to perform logical operations on data stored within said memory; malfunction indicating means which includes a watchdog timer coupled to said microprocessor to detect the occurrence of a preselected periodic event, said malfunction indicating means being operable to indicate a malfunction when said preselected periodic event does not occur within a preselected time period as determined by the timing out of said watchdog timer; and wherein the instructions stored in said memory include a set of instructions which are periodically executed by said microprocessor while said programmable controller is on line to test the operation of said Boolean processor, said set of instructions including: a first subset of instructions which direct the Boolean processor to execute a prescribed sequence of operations; a second subset of instructions which compare the actual state of said Boolean processor with a predetermined state after the execution of said first subset; and a third subset of instructions which enable said indicating means when the actual state of said Boolean processor is not the same as said predetermined state by inhibiting the occurrence of said preselected periodic event.

Claim 9

The improvement as recited in claim 6 in which said indicating means is coupled to an I/O reset line which connects to an I/O interface rack that couples the programmable controller to operating devices on a machine being controlled, and in which a reset signal is generated on said I/O reset line when said watchdog timer times out to decontrol the operating devices coupled to said I/O interface rack.

Claim 10

The improvement as recited in claim 6 in which a visual indicator is coupled to said watchdog timer for energization thereby when the watchdog timer times out.