← Back to Patent Explorer
US4118728A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated circuit structures utilizing conductive buried regions

Assignee: Fairchild Semiconductor Corp
•
Filing: 1976-09-03
•
Granted: 1978-10-03
•
Expires: 1996-09-03
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract In an oxide isolated semiconductor structure having an epitaxial layer formed on a monocrystalline substrate, a buried, laterally extending PN isolation junction in said structure, and oxidized isolation regions extending through said epitaxial layer to said PN isolation junction, thereby to form a plurality of electrically isolated pockets of semiconductor material, a dopant is located in those regions of the semiconductor material directly adjacent the oxidized isolation regions to prevent unwanted current flow called "channeling." The region formed by this dopant is often referred to as the field predeposition region. Typically, to form the field predeposition region, a selected dopant is placed in the exposed surface regions of the epitaxial semiconductor material just prior to the formation of the oxidized isolation regions. The field predeposition and oxidation of the epitaxial semiconductor material also cause the formation of a conductive buried region from that portion of the field predeposition dopant in the epitaxial pockets directly adjacent the oxidized semiconductor material. If desired, a collector sink then may be formed in the epitaxial pocket without disrupting the function of the conductive buried region. The conductive buried region may be utilized to facilitate manufacture of smaller memory circuits than heretofore available, compact junction field effect transistors, and other integrated circuit structures.

Inventors

  • 👤 Robert Berry

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 06:35
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/83; H10D62/00; H10D62/10; H10D62/102; H10D62/112; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0121; H10W10/0125; H10W10/0126; H10W10/10; H10W10/13; H10W20/00; H10W20/01; H10W20/021

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 228 words
A junction field effect transistor formed in a pocket of semiconductor material comprising: the pocket of semiconductor material being a region of semiconductor material electrically isolated from underlying semiconductor material by a laterally extending PN junction, and electrically isolated from adjacent semiconductor material by insulating material, said PN junction defining the bottom of the pocket and said insulating material defining at least part of the walls of the pocket, a source region of first conductivity type formed in the pocket adjacent a first portion of the walls of the pocket, a drain region of first conductivity type formed in the pocket adjacent a second portion of the walls of the pocket, said second portion being nowhere adjacent to said first portion, a gate region of opposite conductivity type formed in the pocket between the source region and the drain region and separating the source region from the drain region, a conductive buried region of first conductivity type disposed between the gate region and a portion of the walls of the pocket, said conductive buried region extending along the walls of the pocket from the source region to the drain region, means for applying electrical signals to the gate region to thereby vary the conductivity of the conductive buried region, means for applying electrical signals to the source region, and means for applying electrical signals to the drain region.
Claim 2
Dependent Claim 228 words
A junction field effect transistor formed in a pocket of semiconductor material comprising: the pocket of semiconductor material being a region of semiconductor material electrically isolated from underlying semiconductor material by a laterally extending PN junction, and electrically isolated from adjacent semiconductor material by insulating material, said PN junction defining the bottom of the pocket and said insulating material defining at least part of the walls of the pocket, a source region of first conductivity type formed in the pocket adjacent a first portion of the walls of the pocket, a drain region of first conductivity type formed in the pocket adjacent a second portion of the walls of the pocket, said second portion being nowhere adjacent to said first portion, a gate region of opposite conductivity type formed in the pocket between the source region and the drain region and separating the source region from the drain region, a conductive buried region of first conductivity type disposed between the gate region and a portion of the walls of the pocket, said conductive buried region extending along the walls of the pocket from the source region to the drain region, means for applying electrical signals to the gate region to thereby vary the conductivity of the conductive buried region, means for applying electrical signals to the source region, and means for applying electrical signals to the drain region.
Claim 3
Dependent Claim 24 words
Structure as in claim 1 further characterized in that said first conductivity type is N type and said opposite conductivity type is P type,
Claim 4
Dependent Claim 24 words
Structure as in claim 1 further characterized in that said first conductivity type is P type and said opposite conductivity type is N type.
Claim 5
Dependent Claim 26 words
Structure as in claim 1 further characterized in that said conductive buried region is of a lower conductivity than said source region and said gate region.
Claim 6
Dependent Claim 18 words
Structure as in claim 1 further characterized in that said insulation comprises oxidized regions of said semiconductor material.
Claim 7
Dependent Claim 18 words
Structure as in claim 1 wherein the conductive buried region is nowhere in contact with the PN junction.
Claim 8
Dependent Claim 25 words
Structure as in claim 1 wherein the conductive buried region is formed beneath the upper surface of each of the source and the drain regions.
Claim 9
Dependent Claim 38 words
Structure as in claim 7 wherein the gate region comprises a first region formed to create the laterally extending PN junction and a second region formed on the upper surface of, and in contact with, said first region.
Claim 10
Dependent Claim 29 words
Structure as in claim 8 wherein the conductive buried region is formed between the walls of the pocket and the interface of the first region and the second region.

References Cited (Backward Citations)

US3600651A Cited
US3648125A Cited
US3975752A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1981-10-02 1982-04-03 1982-10-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1985-10-02 1986-04-03 1986-10-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1989-10-02 1990-04-03 1990-10-03 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag