US4117352A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated clock drive circuit
Assignee: AG Communication Systems Corp
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Filing: 1977-06-09
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Granted: 1978-09-26
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Expires: 1997-06-09
Abstract
Abstract A buffer amplifier, which prevents loading of the input signal, accepts at its input an amplified and equalized pseudo-ternary signal. The output of the buffer amplifier is a-c coupled to the input of a precision differential amplifier, from which two output signals are obtained. One said output signal is representative of the positive pulses and the other said output signal is representative of the negative pulses of the pseudo-ternary signal. These two output signals are both applied to the inputs of a peak detector and a slicer. The d-c output of the peak detector is also applied as one input to the slicer. Separate outputs are obtained from the slicer, one each for the positive and negative pulse inputs, and these two outputs are summed, and the summed output is then amplified to provide a clock driver output.
Inventors
- 👤 Jay A. Thomas
- 👤 Victor J. Stalick, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:08
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/027
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
268 words
In combination, integrated circuit means and discrete circuit means arranged for generating a clock drive signal from a pseudo-ternary signal, which comprises: buffering means having an output, and having an input connected to receive a digital signal; coupling means having an output, and having an input connected to the output of said buffering means; precision gain means having an input connected to the output of said coupling means and having a first output which provides amplified positive excursions and a second output which provides amplified inverted negative excursions of the pseudo-ternary signal; peak detection means having first and second inputs connected, respectively, to the first and second outputs of said precision gain means, and having an output; means for storing the peak amplitude output from said detection means, said storing means having an input connected to the output of said peak detection means and having an output; means for establishing a slicing level amplitude in relation to said peak amplitude, said establishing means having an input connected to the output of said storing means and having an output; means for slicing the digital signal having first and second inputs, respectively, connected to the first and second outputs of said precision gain means, having a third input connected to the output of said establishing means, and having an output; means for adjusting the phase of the sliced signal, having an input connected to the output of said slicing means, and having an output; and means for increasing the output amplitude of said sliced signal having an input connected to the output of said adjusting means and having an output.
Claim 2
Dependent Claim
268 words
In combination, integrated circuit means and discrete circuit means arranged for generating a clock drive signal from a pseudo-ternary signal, which comprises: buffering means having an output, and having an input connected to receive a digital signal; coupling means having an output, and having an input connected to the output of said buffering means; precision gain means having an input connected to the output of said coupling means and having a first output which provides amplified positive excursions and a second output which provides amplified inverted negative excursions of the pseudo-ternary signal; peak detection means having first and second inputs connected, respectively, to the first and second outputs of said precision gain means, and having an output; means for storing the peak amplitude output from said detection means, said storing means having an input connected to the output of said peak detection means and having an output; means for establishing a slicing level amplitude in relation to said peak amplitude, said establishing means having an input connected to the output of said storing means and having an output; means for slicing the digital signal having first and second inputs, respectively, connected to the first and second outputs of said precision gain means, having a third input connected to the output of said establishing means, and having an output; means for adjusting the phase of the sliced signal, having an input connected to the output of said slicing means, and having an output; and means for increasing the output amplitude of said sliced signal having an input connected to the output of said adjusting means and having an output.
Claim 3
Dependent Claim
86 words
Apparatus according to claim 1 wherein said buffering means further comprises: a power source providing positive and negative supply voltages; a first bias source having an input connected to the negative supply voltage and providing at its output a reference current; and a buffer amplifier comprising a first integrated circuit transistor having base, emitter and collector, said base being connected to receive the pseudo-ternary signal, said collector connected to said positive supply source and said emitter being connected to the output of said first bias source.
Claim 4
Dependent Claim
13 words
Apparatus according to claim 2 wherein said coupling means further comprises a capacitor.
Claim 5
Dependent Claim
116 words
Apparatus according to claim 3 wherein said precision gain means further comprises: a first integrated circuit differential amplifier having one input connected to said a-c coupling means, having second and third inputs and said first and second outputs; a second bias source having an input connected to said negative supply source and providing a reference current into said second input of said first integrated circuit differential amplifier; and a third bias source having an input connected to said positive supply and providing bias voltage compensation, which is equal to the base emitter voltage drop of a transistor in said differential pair, said third source having an output connected to the third input of said differential pair.
Claim 6
Dependent Claim
108 words
Apparatus according to claim 4 wherein said peak detection means further comprises: a first integrated circuit transistor amplifier for amplifying the positive excursions of the pseudo-ternary pulses having an input connected to receive the positive excursions from the first output of the first integrated circuit differential amplifier and having an output; and a second integrated circuit transistor amplifier for amplifying the inverted negative excursions of the input pseudo-ternary pulses having an input connected to receive the inverted negative excursions from the second output of the first integrated circuit differential amplifier and having an output, said output being connected to the output of said first integrated circuit transistor amplifier.
Claim 7
Dependent Claim
33 words
Apparatus according to claim 5 wherein said means for storing further comprises a capacitor and associated circuitry having a time constant which will hold the peak signal input for a full slicing cycle.
Claim 8
Dependent Claim
114 words
Apparatus according to claim 6 wherein said means for establishing a slicing level amplitude further comprises: a fourth bias source having an input connected to the negative supply source and providing a reference current at its output; a second integrated circuit differential amplifier connected as a voltage follower, having an input connected to receive said peak signal, having a second input connected to the output of said fourth bias source, and having an output; a voltage divider having an input connected to the output of said second differential amplifier and providing a slicing level signal, V s , at its output; and a capacitor connected between the output of said voltage divider and ground.
Claim 9
Dependent Claim
104 words
Apparatus according to claim 7 wherein said means for slicing further comprises: a second integrated circuit transistor having a base connected to receive one polarity of the received pseudo-ternary signal, a collector connected to the positive power supply source and having the emitter connected to the slicing level voltage output; and a third integrated circuit transistor having a base connected to receive the opposite polarity of the pseudo-ternary signal, having a collector connected to the positive supply source and also connected to the collector of said second integrated circuit transistor, and having its emitter connected to the emitter of said second integrated circuit transistor.
Claim 10
Dependent Claim
21 words
Apparatus according to claim 8 wherein said means for adjusting the phase further comprises an adjustable low-Q tuned phase shifting network.
Claim 11
Dependent Claim
22 words
Apparatus in accordance with claim 9 wherein said means for increasing the output amplitude further comprises a fourth integrated circuit transistor amplifier.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-09-25 | 1982-03-27 | 1982-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-09-25 | 1986-03-27 | 1986-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-09-25 | 1990-03-27 | 1990-09-26 | $7700.00 | Window Closed / Lapsed |