US3707683A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Timing recovery circuit for use in modified duobinary transmission system
Assignee: AG Communication Systems Corp
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Filing: 1971-11-15
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Granted: 1972-12-26
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Expires: 1991-11-15
Abstract
Abstract A circuit for producing a timing signal from a modified duobinary data signal. This data signal is capacitively coupled through four full-wave rectifiers that are connected in series. The outputs of the third and fourth rectifiers are DC coupled through an adder to a bandpass filter which passes a timing signal that has a fixed phase relationship with respect to the timing signal that was originally employed to produce the modified duobinary signal. The filtered signal is delayed, squared in a limiter, and applied to a zero crossing detector which produces a train of clock timing pulses.
Inventors
- 👤 Berton E Dotter Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 13:29
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0054; H04L7/0066
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
72 words
A circuit for recovering a timing signal from a modified duobinary data signal that is produced with clock timing pulses having a prescribed pulse repetition frequency comprising a plurality of full-wave rectifiers connected in series, first means for coupling the modified duobinary signal to the input of the first one of said rectifiers, and means for selecting the recovered timing signal from the output signal of the last one of said rectifiers.
Claim 2
Dependent Claim
72 words
A circuit for recovering a timing signal from a modified duobinary data signal that is produced with clock timing pulses having a prescribed pulse repetition frequency comprising a plurality of full-wave rectifiers connected in series, first means for coupling the modified duobinary signal to the input of the first one of said rectifiers, and means for selecting the recovered timing signal from the output signal of the last one of said rectifiers.
Claim 3
Dependent Claim
47 words
The circuit according to claim 1 wherein said selecting means comprises a filter having a narrow passband for passing a signal component in the output signal of the last one of said rectifiers having a frequency equal to the pulse repetition frequency of the clock timing pulses.
Claim 4
Dependent Claim
9 words
The circuit according to claim 1 including three rectifiers.
Claim 5
Dependent Claim
9 words
The circuit according to claim 1 including four rectifiers.
Claim 6
Dependent Claim
50 words
The circuit according to claim 4 wherein said selecting means comprises a filter having a narrow passband with a center frequency equal to the prescribed pulse repetition frequency and second means coupling the output signals of the third and fourth ones of said rectifiers to the input of said filter.
Claim 7
Dependent Claim
27 words
The circuit according to claim 5 including means for producing an output pulse when the amplitude of the output of said filter passes a prescribed reference level.
Claim 8
Dependent Claim
15 words
The circuit according to claim 6 wherein said producing means includes a zero crossing detector.
Claim 9
Dependent Claim
36 words
The circuit according to claim 5 including third means for AC coupling the modified duobinary signal to said first rectifier and for AC coupling said rectifiers together to establish a reference level through the outputs thereof.
Claim 10
Dependent Claim
36 words
The circuit according to claim 1 wherein each of said rectifiers includes means for establishing an offset voltage associated with the rectifier output signal to compensate for the voltage drop caused by the rectifying elements thereof.
Claim 11
Independent Claim
73 words
The method of recovering a timing signal from a modified duobinary data signal that is produced with cLock timing pulses having a prescribed pulse repetition frequency, comprising the steps of performing a plurality of successive full-wave rectifications of the modified duobinary signal, and filtering a multiply rectified signal in a circuit having a narrow passband passing a signal having a frequency equal to the prescribed pulse repetition frequency of the clock timing pulses.
Claim 12
Independent Claim
73 words
The method of recovering a timing signal from a modified duobinary data signal that is produced with cLock timing pulses having a prescribed pulse repetition frequency, comprising the steps of performing a plurality of successive full-wave rectifications of the modified duobinary signal, and filtering a multiply rectified signal in a circuit having a narrow passband passing a signal having a frequency equal to the prescribed pulse repetition frequency of the clock timing pulses.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-12-26 | 1976-06-26 | 1976-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-12-26 | 1980-06-26 | 1980-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-12-26 | 1984-06-26 | 1984-12-26 | $7700.00 | Window Closed / Lapsed |