US3567959A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase-locked pulse generator with frequency maintaining function
Assignee: NEC Corp
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Filing: 1967-10-16
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Granted: 1971-03-02
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Expires: 1987-10-16
Abstract
Abstract A phase-locked pulse generator for producing clock pulses for reception of digital signals including timing information of varying density and comprising a sampling type phase comparator and a low pass filter for temporarily holding, in the case of a reduction in the timing information density, the timing information detected by the phase comparator. Due to this holding action, the frequency of the pulse generator is controlled by the output of the low pass filter and is maintained substantially unchanged even when the timing information is not continually included in the digital signal.
Inventors
- 👤 Hisashi Kaneko
- 👤 Atsushi Tomozawa
- 👤 Yukio Takimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 17:27
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/027
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
262 words
A phase-locked pulse generator arrangement comprising timing information extraction means for deriving a timing information pulse from an input digital signal in which the occurrence probability of waveform transitions is not constant; a pulse generator for generating a pulse train having a repetition frequency varying in response to a low frequency control signal, sampling gate means having a first input coupled to said timing information extraction means and a second input coupled to said pulse generator, said sampling means having an open and closed period in response to the state of said information pulse, said sampling means comprising means for generating a sampled signal corresponding to the phase difference between said pulse train and said timing information pulse, a low pass filter coupled to the output of said sampling gate means and having a charging circuit for extracting the low frequency component from said sampled signal and for supplying said component as said low frequency control signal to said pulse generator, means for establishing first and second discharge paths for said filter charging circuit in response to the open and closed periods of said sampling gate means such that the time constant of said low pass filter charging circuit in the open period of said sampling gate means is greater than its time-constant in the closed period of said sampling gate means and greater than the longest expected succeeding time interval of one of the states of said input digital signal; and an output terminal for deriving the output of said pulse generator as the timing pulse of said input digital signal.
Claim 2
Dependent Claim
262 words
A phase-locked pulse generator arrangement comprising timing information extraction means for deriving a timing information pulse from an input digital signal in which the occurrence probability of waveform transitions is not constant; a pulse generator for generating a pulse train having a repetition frequency varying in response to a low frequency control signal, sampling gate means having a first input coupled to said timing information extraction means and a second input coupled to said pulse generator, said sampling means having an open and closed period in response to the state of said information pulse, said sampling means comprising means for generating a sampled signal corresponding to the phase difference between said pulse train and said timing information pulse, a low pass filter coupled to the output of said sampling gate means and having a charging circuit for extracting the low frequency component from said sampled signal and for supplying said component as said low frequency control signal to said pulse generator, means for establishing first and second discharge paths for said filter charging circuit in response to the open and closed periods of said sampling gate means such that the time constant of said low pass filter charging circuit in the open period of said sampling gate means is greater than its time-constant in the closed period of said sampling gate means and greater than the longest expected succeeding time interval of one of the states of said input digital signal; and an output terminal for deriving the output of said pulse generator as the timing pulse of said input digital signal.
Claim 3
Dependent Claim
72 words
The invention described in claim 1 wherein said timing information extraction means comprises: a pulse transformer having its primary connected to receive said input digital signal; a differential circuit connected to the secondary of said transformer; a rectifier circuit connected to receive the output from said differential circuit; a multivibrator connected to receive the output from said rectifier circuit; and said timing information pulse being present at the output of said multivibrator.
Claim 4
Dependent Claim
148 words
The invention described in claim 1 wherein said sampling gate means comprises: a logical circuit for receiving said timing information pulse at one input terminal thereof and said pulse train at another input terminal thereof; means in said logical circuit for providing from the input signal pulses thereto a summation output signal and a product output signal at first and second output terminals thereof, respectively; said sampling gate means having a common output terminal connected to the input of said low pass filter; a first NOT circuit transistor and a first Diode connected in series between said first output terminal and said common output terminal; a first resistor connected between the collector of said first transistor and the source of potential therefor; and a second NOT circuit transistor, a second resistor and a second diode connected in series between said second output terminal and said common output terminal.
Claim 5
Dependent Claim
35 words
The invention described in claim 3 wherein said low pass filter includes a third resistor and a capacitor connected in series between said common output terminal and ground, and a fourth resistor bridging said capacitor.
Claim 6
Dependent Claim
22 words
The invention described in claim 4 which further includes a first time constant charging circuit and a second time constant discharging circuit.
Claim 7
Dependent Claim
57 words
The invention described in claim 5 wherein: said first time constant charging circuit comprises a series circuit including said first resistor, said first diode, said third resistor and said capacitor; and said second time constant discharging circuit comprises a series circuit including said third resistor, said second diode, said second resistor, said second transistor and said capacitor.
Claim 8
Dependent Claim
226 words
A phase-locked pulse generator arrangement comprising: means for deriving a timing information pulse from an input digital signal; a first NAND circuit having a first input terminal for receiving said timing information pulse, said circuit also having a second input terminal; a first diode connected between the output of said first NAND circuit and a common terminal; a low pass filter having its input connected to said common terminal; a variable frequency pulse oscillator for generating a pulse train at the output thereof; means for coupling the output of said low pass filter to the input of said oscillator; means for coupling the pulse train at the output of said oscillator to the second input terminal of said first NAND circuit; a first NOT circuit for also receiving said pulse train from the output of said oscillator; a second NAND circuit also having first and second input terminals; means for coupling said timing information pulse to the first input terminal of said second NAND circuit; means for coupling the output from said first NOT circuit to the second input terminal of said second NAND circuit; a second NOT circuit coupled to receive the output from said second NAND circuit; and and a second diode connected between the output of said second NOT circuit and said common terminal, whereby the frequency of said oscillator is closely controlled.
Claim 9
Dependent Claim
226 words
A phase-locked pulse generator arrangement comprising: means for deriving a timing information pulse from an input digital signal; a first NAND circuit having a first input terminal for receiving said timing information pulse, said circuit also having a second input terminal; a first diode connected between the output of said first NAND circuit and a common terminal; a low pass filter having its input connected to said common terminal; a variable frequency pulse oscillator for generating a pulse train at the output thereof; means for coupling the output of said low pass filter to the input of said oscillator; means for coupling the pulse train at the output of said oscillator to the second input terminal of said first NAND circuit; a first NOT circuit for also receiving said pulse train from the output of said oscillator; a second NAND circuit also having first and second input terminals; means for coupling said timing information pulse to the first input terminal of said second NAND circuit; means for coupling the output from said first NOT circuit to the second input terminal of said second NAND circuit; a second NOT circuit coupled to receive the output from said second NAND circuit; and and a second diode connected between the output of said second NOT circuit and said common terminal, whereby the frequency of said oscillator is closely controlled.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-01 | 1974-08-31 | 1975-03-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-01 | 1978-08-31 | 1979-03-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-01 | 1982-08-31 | 1983-03-02 | $7700.00 | Window Closed / Lapsed |