US4027178A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for generating synchronization signals
Assignee: Telent Technologies Services Ltd
•
Filing: 1975-12-10
•
Granted: 1977-05-31
•
Expires: 1995-12-10
Abstract
Abstract A circuit for generating synchronization signals from a digital data pulse train having a bit period T and conveying pulses in non-return-to-zero form. The circuit comprising (i) a rectifier device arranged to fullwave rectify the digital data pulse train, (ii) an oscillatory circuit tuned to oscillate with period T and stimulated by the transitions of a waveform produced by the fullwave rectifier device and (iii) a peak detector arranged to produce a bias signal which is proportional to the amplitude of the output of the oscillatory circuit. The bias signal being active upon the fullwave rectifier device to stabilize the amplitude of the waveform produced by the oscillatory circuit.
Inventors
- 👤 Douglas Stanley Larner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:19
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B27/00; G11B27/10; G11B27/19; G11B27/28; G11B27/30; H; H04; H04L; H04L7/00; H04L7/02; H04L7/027
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
127 words
A circuit for generating synchronization signals from a digital data pulse train handling non-return-to-zero bits having a bit period of T, the circuit comprising in combination, a fullwave rectifier means for receiving a digital data pulse train and producing a rectified output waveform corresponding to the digital data pulse train transitions and including a bias signal responsive means for controlling the amplitude of said rectified output waveform, an oscillatory circuit tuned to oscillate with period T, fed by said rectifier output waveform and stimulated by the transitions of said rectified output waveform to produce said synchronization signals and a bias level generator means for generating a bias signal proportional to the amplitude of said synchronization signals, and for applying the same to said bias signal responsive means.
Claim 2
Dependent Claim
127 words
A circuit for generating synchronization signals from a digital data pulse train handling non-return-to-zero bits having a bit period of T, the circuit comprising in combination, a fullwave rectifier means for receiving a digital data pulse train and producing a rectified output waveform corresponding to the digital data pulse train transitions and including a bias signal responsive means for controlling the amplitude of said rectified output waveform, an oscillatory circuit tuned to oscillate with period T, fed by said rectifier output waveform and stimulated by the transitions of said rectified output waveform to produce said synchronization signals and a bias level generator means for generating a bias signal proportional to the amplitude of said synchronization signals, and for applying the same to said bias signal responsive means.
Claim 3
Dependent Claim
34 words
A circuit for generating synchronization signals according to claim 1 wherein said fullwave rectifier means includes a differential amplifier employing emitter coupled transisitors fed from a current source including said bias signal responsive means.
Claim 4
Dependent Claim
46 words
A circuit for generating synchronization signals according to claim 1 wherein said bias level generator means comprises a peak detector means for producing a voltage proportional to the amplitude of said synchronization signals and a differential amplifier means for comparing said voltage to a reference voltage.
Claim 5
Dependent Claim
51 words
A circuit for generating synchronization signals according to claim 2, wherein said bias signal responsive means comprises a transistor having its collector electrode connected to said emitter coupled transistors, its emitter connected to a voltage source, and its base connected to the bias level generator means to receive the bias signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-05-30 | 1980-11-29 | 1981-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-05-30 | 1984-11-29 | 1985-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-05-30 | 1988-11-29 | 1989-05-31 | $7700.00 | Window Closed / Lapsed |