US3609408A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock pulse generator
Assignee: RCA Corp
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Filing: 1969-09-30
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Granted: 1971-09-28
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Expires: 1989-09-30
Abstract
Abstract Signals such as pulses derived from binary data signals are employed to excite a tuned circuit. When the frequency nf to which the tuned circuit is tuned differs from n times the actual frequency f'' of the binary data signals, a control signal is produced which is employed to tune the tuned circuit in a sense and amount to reduce the control signal to zero. Clocking signals synchronous with the binary data signals may be derived from the tuned circuit.
Inventors
- 👤 Lewis Rand Motisher
- 👤 Emil Engel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:34
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/027; G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
184 words
A circuit for producing clock signals which are synchronous with binary signals comprising, in combination: a source of signals of the type in which each change in signal level represents a binary digit, said source being subject to drift; a tuned circuit tuned to frequency nf, where n is some integer and f is the nominal frequency of said signals representing binary digits; pulse producing means coupled to said source for translating each change in signal level to a pulse of the same polarity; means for applying said pulses to said tuned circuits; clock signal producing means coupled to said tuned circuit for translating the oscillations produced thereby to a square wave and its complement; means for comparing the phase of said square wave with that of said pulses for developing a first direct voltage level; means for comparing the phase of the complement of said square wave with that of said pulses for developing a second direct voltage level; and means responsive to said first and second voltage levels for tuning said tuned circuit in a sense to make said two levels equal.
Claim 2
Dependent Claim
184 words
A circuit for producing clock signals which are synchronous with binary signals comprising, in combination: a source of signals of the type in which each change in signal level represents a binary digit, said source being subject to drift; a tuned circuit tuned to frequency nf, where n is some integer and f is the nominal frequency of said signals representing binary digits; pulse producing means coupled to said source for translating each change in signal level to a pulse of the same polarity; means for applying said pulses to said tuned circuits; clock signal producing means coupled to said tuned circuit for translating the oscillations produced thereby to a square wave and its complement; means for comparing the phase of said square wave with that of said pulses for developing a first direct voltage level; means for comparing the phase of the complement of said square wave with that of said pulses for developing a second direct voltage level; and means responsive to said first and second voltage levels for tuning said tuned circuit in a sense to make said two levels equal.
Claim 3
Dependent Claim
28 words
A circuit as set forth in claim 1, wherein said means for tuning said tuned circuit includes a pair of varactor diodes serving as electronically controllable impedance elements.
Claim 4
Dependent Claim
56 words
A circuit as set forth in claim 1, wherein the last-named means includes a differential amplifier having a pair of input signal terminals, a capacitor connected between these terminals, means for applying said first direct voltage level to one of said terminals, and means for applying said Second direct voltage level to the other said terminal.
Claim 5
Dependent Claim
41 words
A circuit as set forth in claim 3, further including an electronically controllable impedance as one of the elements of said tuned circuit, and a low-pass filter connected between the output terminal of said differential amplifier and said electronically controllable impedance.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-09-27 | 1975-03-29 | 1975-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-09-27 | 1979-03-29 | 1979-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-09-27 | 1983-03-29 | 1983-09-28 | $7700.00 | Window Closed / Lapsed |