Patent US4112514A successfully refreshed from Google Patents.
US4112514A
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US
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Memory with dynamic information storage
Assignee: Digital Equipment Corp
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Filing: 1977-01-17
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Granted: 1978-09-05
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Expires: 1997-01-17
Abstract
Abstract A refreshing organization for use in a main memory with dynamic information storage. In the case of a memory matrix, for example, each row of bit positions is addressed by first sub-address signals, with the result that a refreshing operation is performed for the complete information of the relevant row. Within a row, each bit position is addressed by second sub-address signals. A second memory is provided which includes one word position for each bit row of the main memory. The second memory has a comparatively short memory cycle. During the first half of the "slow" memory cycle, a word of the second memory is addressed by the first sub-address signals and is filled with predetermined information. During the second half of the "slow" memory cycle, a next word of the second memory is addressed during each cycle by the position of an address counter. The stored word which is addressed is then read. The output register is constructed as a counter; the information read is increased by 1 and is written back. A carry output signal of the output register can reserve the next "slow" cycle of the main memory for the execution of a refreshing operation at an address of the main memory which corresponds to the position of the address counter.
Inventors
- 👤 Gerrit Adriaan Spoelder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 07:48
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/24
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
354 words
A memory system for operation with a user device, comprising: a first memory comprising memory sections for information storage, and having a first memory cycle time; a first address line connected to said first memory for receiving first partial address signals from said user device for addressing a memory section thereof, and controlling a refresh operation therein; a second address line connected to said first memory for receiving second partial address signals from said user device for addressing a portion of said memory section addressed by said first partial address signals, an information transport line connected to said first memory for transporting information signals between said user device and said memory section portion addressed by said first and second partial address signals; a second memory having a second memory cycle time substantially shorter than said first memory cycle time and having a plurality of memory positions each corresponding to a predetermined one of said memory sections; a third address line connected to said second memory for receiving said first partial address signals in parallel with said first address line, a data register having an input for receiving an incrementation signal and an output; control means habing a first state and a second state, including an address-counter for said second memory, and a clock for cycling said control means between said states, said control means in said first state being operative for transmitting said first partial address signals to said second memory and for writing predetermined information into a memory position thus addressed, said control means in said second state being operative for transmitting the contents of said address counter after an incrementation thereof to said second memory for controlling a read-write cycle for the memory position thus addressed under further generation of an incrementation signal for writing back an incremented information, an output signal of said data register blocking the next subsequent transition to said first state, whereby said first memory thereupon is addressed by the contents of said address counter in lieu of by said first partial address signals, a memory section thus addressed being refreshed at least once within its reliability period.
Claim 2
Dependent Claim
354 words
A memory system for operation with a user device, comprising: a first memory comprising memory sections for information storage, and having a first memory cycle time; a first address line connected to said first memory for receiving first partial address signals from said user device for addressing a memory section thereof, and controlling a refresh operation therein; a second address line connected to said first memory for receiving second partial address signals from said user device for addressing a portion of said memory section addressed by said first partial address signals, an information transport line connected to said first memory for transporting information signals between said user device and said memory section portion addressed by said first and second partial address signals; a second memory having a second memory cycle time substantially shorter than said first memory cycle time and having a plurality of memory positions each corresponding to a predetermined one of said memory sections; a third address line connected to said second memory for receiving said first partial address signals in parallel with said first address line, a data register having an input for receiving an incrementation signal and an output; control means habing a first state and a second state, including an address-counter for said second memory, and a clock for cycling said control means between said states, said control means in said first state being operative for transmitting said first partial address signals to said second memory and for writing predetermined information into a memory position thus addressed, said control means in said second state being operative for transmitting the contents of said address counter after an incrementation thereof to said second memory for controlling a read-write cycle for the memory position thus addressed under further generation of an incrementation signal for writing back an incremented information, an output signal of said data register blocking the next subsequent transition to said first state, whereby said first memory thereupon is addressed by the contents of said address counter in lieu of by said first partial address signals, a memory section thus addressed being refreshed at least once within its reliability period.
Claim 3
Dependent Claim
52 words
A memory system as claimed in claim 1, further comprising comparison means connected to said address counter for receiving the position of the address counter and the first sub-address signals from the user device, a correspondence signal therein causing the conduction of the first sub-address signals then received from the user device.
References Cited (Backward Citations)
US3737879A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-09-04 | 1982-03-06 | 1982-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-09-04 | 1986-03-06 | 1986-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-09-04 | 1990-03-06 | 1990-09-05 | $7700.00 | Window Closed / Lapsed |