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US4109243A
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Data sequence display system and time-compression system therefor
Assignee: American Optical Corp
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Filing: 1976-04-26
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Granted: 1978-08-22
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Expires: 1996-04-26
Abstract
Abstract A system for the cyclical time-compression of a signal waveform, particularly applicable to displays. Continuous input data is temporarily stored, as in a recirculating memory, during the trace and retrace phases (B & A) of a processing or display operation. The stored data is subsequently read out in time-compressed form during the trace phase (B) of the cycle. The average rate at which data is read out of storage is faster than the average rate at which it is entered, the ratio of average readout rate to average entry rate being the compression ratio of the system and corresponding herein with the ratio of a full display sweep cycle to the trace portion of that cycle such that the initial waveform, time-compressed, is displayed in its entirety. In an illustrated embodiment, the data is entered into a recirculating memory at a rate resulting in apparent precession of the data in memory. When the memory is "full", data is read out at a rate, here syncopated, which on average is faster than the rate at which it enters. In this embodiment, the time-compression ratio is essentially n+1/n, where n is an integer representative of the length of the trace phase of a trace-retrace display cycle. The data samples read out of memory at a syncopated rate are retimed to avoid distortion in the output waveform.
Inventors
- 👤 Christopher Cameron Day
- 👤 Robert Lee Cannon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:00
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/08; G06F5/085; A; A61; A61B; A61B5/00; A61B5/24; A61B5/316; A61B5/318; A61B5/333; A61B5/336; A61B5/337; A61B5/72; A61B5/7232; G01; G01D; G01D9/00; G01R; G01R13/00; G01R13/20; G01R13/22; G01R13/34; G01R13/345
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
251 words
A system for the cyclical time-compression of a signal waveform comprising: a recirculating memory of predetermined time-quantized length, said memory providing a storage delay corresponding with the product of said predetermined time-quantized length and the number of passes through said memory; means having successive samples of the signal waveform extended thereto and being responsive to first timing signals for entering respective said samples of the signal waveform into said memory; means for generating and applying a plurality of said first timing signals to said data entry control means throughout a time-compression cycle, said first timing signals recurring at an interval corresponding with the interval between successive samples of the signal waveform, said first timing signals having an interval such as to cause precession of the samples in the memory, and a predetermined number of the samples being entered in said memory during a first fraction of each time-compression cycle; means responsive to second timing signals for selectively interrogating said memory and providing read out of the respective interrogated samples; and means for generating and applying said second timing signals to said memory interrogation means following a time delay comprising said first fraction of each time-compression cycle, the remaining fraction of each said time-compression cycle being a compressed-time cycle in which the timing of said second timing signals is such that the storage delay of said recirculating memory is decremented from a maximum to a minimum over said compressed-time cycle whereby said interrogated samples cumulatively substantially represent the signal waveform in time-compression.
Claim 2
Independent Claim
251 words
A system for the cyclical time-compression of a signal waveform comprising: a recirculating memory of predetermined time-quantized length, said memory providing a storage delay corresponding with the product of said predetermined time-quantized length and the number of passes through said memory; means having successive samples of the signal waveform extended thereto and being responsive to first timing signals for entering respective said samples of the signal waveform into said memory; means for generating and applying a plurality of said first timing signals to said data entry control means throughout a time-compression cycle, said first timing signals recurring at an interval corresponding with the interval between successive samples of the signal waveform, said first timing signals having an interval such as to cause precession of the samples in the memory, and a predetermined number of the samples being entered in said memory during a first fraction of each time-compression cycle; means responsive to second timing signals for selectively interrogating said memory and providing read out of the respective interrogated samples; and means for generating and applying said second timing signals to said memory interrogation means following a time delay comprising said first fraction of each time-compression cycle, the remaining fraction of each said time-compression cycle being a compressed-time cycle in which the timing of said second timing signals is such that the storage delay of said recirculating memory is decremented from a maximum to a minimum over said compressed-time cycle whereby said interrogated samples cumulatively substantially represent the signal waveform in time-compression.
Claim 3
Dependent Claim
58 words
The time-compression system of claim 1 wherein said data entry control means and said memory interrogation means respectively have fixed access to said recirculating memory, and said second timing signals occur successively in said compressed-time cycle following first and second intervals of different length thereby to effect said decrementation of the apparent time-quantized length of said recirculating memory.
Claim 4
Dependent Claim
94 words
The time-compression system of claim 2 wherein the time-quantized length of said recirculating memory comprises a predetermined number of serially connected stages of storage clocked at a predetermined shift rate, said first interval between successive said second timing signals corresponds with that of said first timing signals thereby to maintain a particular apparent time-quantized length of said recirculating memory, and said second timing signals occurring at said second interval being regressed one stage of memory storage relative to the respective immediately preceding second timing signal thereby decrementing the apparent time-quantized length of said memory.
Claim 5
Dependent Claim
54 words
The time-compression system of claim 3 wherein the number of said second timing signals occurring within said compressed-time cycle is substantially the same as the number of said first timing signals occurring within said time-compression cycle thereby to provide readout of substantially all of the samples entered into said memory during said time-compression cycle.
Claim 6
Dependent Claim
52 words
The time-compression system of claim 4 wherein the ratio of the number of said second timing signals occurring at said second interval relative to those occurring at said first interval within a said time-compression cycle corresponds with the ratio of said first fraction to said remaining fraction of a said time-compression cycle.
Claim 7
Dependent Claim
33 words
The time compression system of claim 4 wherein said first and second intervals at which said second timing signals occur are interspersed, thereby resulting in a rhythmic pattern of said second timing signals.
Claim 8
Dependent Claim
67 words
The time-compression system of claim 6 wherein said interspersal of said first and second intervals between successivve said second timing signals comprises each "n" successive second timing signals occurring at said first interval being immediately followed by a single second timing signal occurring at said second interval, where "n" represents the ratio of the length of said remaining fraction to said first fraction of said time-compression cycle.
Claim 9
Dependent Claim
12 words
The time compression system of claim 7 wherein "n" is an integer.
Claim 10
Dependent Claim
97 words
The time-compression system of claim 2 wherein the time-quantized length of said recirculating memory comprises the product of a predetermined number of stages of storage and the period of the clock signal applied to said storage stages for the serial shift of samples stored therein, and the interval at which said first timing signals recur is greater than the time-quantized length of said memory by the interval commensurate with a single repetition of the storage shift clock signal whereby said samples in said memory precess one storage stage for each successive one of said first timing signals.
Claim 11
Dependent Claim
47 words
The time-compression system of claim 8 wherein the time-quantized length of said memory and the interval between successive said first timing signals are selected such that said memory is substantially exactly filled with successive samples of the signal waveform during said first fraction of said time-compression cycle.
Claim 12
Dependent Claim
68 words
The time-compression system of claim 1 including first means for converting the magnitude of said signal waveform to a digital sample, means for operating periodically said first converting means at the repetition rate of said first timing signals whereby said waveform samples are said digital samples, and second means for converting said digital samples in time-compression from said memory interrogation means to a respective time-compressed analog signal waveform.
Claim 13
Dependent Claim
121 words
The time-compression system of claim 11 wherein said memory interrogation means includes first storage means responsive to said second timing signals for selectively interrogating said memory and temporarily storing the respective interrogated digital sample, second storage means having the output of said first storage means extended thereto and responsive to third timing signals for temporarily storing the respective digital sample appearing at said first latch, and means for generating and applying said third timing signals to said second storage means during said compressed time cycle, said third timing signals recurring at substantially constant intervals and in substantially the same number as said second timing signals during said compressed-time cycle thereby to equalize the timing of said interrogated digital samples being readout.
Claim 14
Dependent Claim
77 words
The time-compression system of claim 1 wherein the signal waveform is for display by means having a plurality of two phase display cycles, said first fraction of each said time-compression cycle corresponding with one phase of each said display cycle, and each said compressed-time cycle corresponding with the other phase of each said display cycle thereby to display the signal waveform in time-compression substantially in its entirety during the said other phases of respective said display cycles.
Claim 15
Dependent Claim
257 words
In a signal waveform processing and display system, display means responsive to a cyclical control signal for alternately displaying and interrupting the display of a particular input data signal extended thereto; means for generating said display control signal; means providing a continuous source data waveform signal for display by said display means; means for periodically sampling the waveform to provide sequential waveform data samples; memory means for storing said data samples for differing periods of time until respective readout; means for continuously entering a plurality of said data samples sequentially into said memory at a first average rate throughout each of a succession of time-compression cycles of predetermined duration; and means responsive to said data samples and said display control signal for cyclically time-compressing said source waveform signal to cyclically present said source waveform in time compression during only the displaying phase of said display control signal as said particular input data signal to said display means, said time-compression means including means for interrogating said memory throughout only a predetermined latter portion of the duration of each time-compression cycle at a second average rate having the same ratio to said first average rate as the duration of said time-compression cycle has to the duration of said latter portion thereof to read respective said data samples out of memory in the same sequence as entered whereby data samples are read out of memory at an average rate faster than said entry rate such that said source data waveform is displayed substantially in its entirety on said display means.
Claim 16
Dependent Claim
257 words
In a signal waveform processing and display system, display means responsive to a cyclical control signal for alternately displaying and interrupting the display of a particular input data signal extended thereto; means for generating said display control signal; means providing a continuous source data waveform signal for display by said display means; means for periodically sampling the waveform to provide sequential waveform data samples; memory means for storing said data samples for differing periods of time until respective readout; means for continuously entering a plurality of said data samples sequentially into said memory at a first average rate throughout each of a succession of time-compression cycles of predetermined duration; and means responsive to said data samples and said display control signal for cyclically time-compressing said source waveform signal to cyclically present said source waveform in time compression during only the displaying phase of said display control signal as said particular input data signal to said display means, said time-compression means including means for interrogating said memory throughout only a predetermined latter portion of the duration of each time-compression cycle at a second average rate having the same ratio to said first average rate as the duration of said time-compression cycle has to the duration of said latter portion thereof to read respective said data samples out of memory in the same sequence as entered whereby data samples are read out of memory at an average rate faster than said entry rate such that said source data waveform is displayed substantially in its entirety on said display means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-08-21 | 1982-02-20 | 1982-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-08-21 | 1986-02-20 | 1986-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-08-21 | 1990-02-20 | 1990-08-22 | $7700.00 | Window Closed / Lapsed |