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US3855424A Expired / Lapsed US ⏱️ 0.0 years remaining

Information processor for changing tempo of playback from the recorded tempo

Assignee: US Philips Corp
•
Filing: 1973-01-30
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Granted: 1974-12-17
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Expires: 1993-01-30
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Abstract

Abstract Accelerated or retarded signal playback is accomplished by writing the information alternately into one shift register at one clock frequency and reading out from the other shift register at another clock frequency. Feedback from a selectable last stage ''''main'''' output or from an ''''auxiliary'''' output intermediate stage of a shift register permits repetition of differing portions of the signal segment, to provide improved quality of reproduction for burst signals such as plosive sounds in speech.

Inventors

  • 👤 P Tharmaratnam
  • 👤 J Cluwen

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 03:58
CPC Classifications
G; G10; G10L; G10L21/00; G10L21/04; G11; G11B; G11B27/00; G11B27/005

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 271 words
A circuit arrangement for playing back recorded information in a tempo which differs from the original recording tempo, and particularly for playing back retarded or accelerated speech while maintaining the correct pitch, said circuit arrangement comprising: a first shift register having an input, an output, and an auxiliary output; a second shift register having an input, an output, and an auxiliary output; means for supplying information in a desired tempo to said registers; a first electronic switch disposed between said registers and said information supplying means to alternately apply said information to said registers; a second electronic switch operated in phase opposition to said first switch, said second electronic switch connected to said registers for alternatively deriving an output signal therefrom; means for supplying said registers with clock pulses for advancing information therethrough; first switching means disposed between said registers and said clock pulse supplying means, for alternately, but in phase opposition, applying said clock pulses to said registers, frequencies of said clock pulses jumping from one value to another at each change-over of said switching means, a ratio of these frequencies being equal to a speed ratio between the speed at which said information is applied to the shift registers and the speed at which said information is recorded; and second switching means connected to respective registers, for connecting the respective auxiliary output of each register to the input of said respective register, said respective auxiliary outputs being partway along said registers between said inputs and said outputs such that said information at said auxiliary output is less advanced in said register than that corresponding to said respective output signal.
Claim 2
Dependent Claim 271 words
A circuit arrangement for playing back recorded information in a tempo which differs from the original recording tempo, and particularly for playing back retarded or accelerated speech while maintaining the correct pitch, said circuit arrangement comprising: a first shift register having an input, an output, and an auxiliary output; a second shift register having an input, an output, and an auxiliary output; means for supplying information in a desired tempo to said registers; a first electronic switch disposed between said registers and said information supplying means to alternately apply said information to said registers; a second electronic switch operated in phase opposition to said first switch, said second electronic switch connected to said registers for alternatively deriving an output signal therefrom; means for supplying said registers with clock pulses for advancing information therethrough; first switching means disposed between said registers and said clock pulse supplying means, for alternately, but in phase opposition, applying said clock pulses to said registers, frequencies of said clock pulses jumping from one value to another at each change-over of said switching means, a ratio of these frequencies being equal to a speed ratio between the speed at which said information is applied to the shift registers and the speed at which said information is recorded; and second switching means connected to respective registers, for connecting the respective auxiliary output of each register to the input of said respective register, said respective auxiliary outputs being partway along said registers between said inputs and said outputs such that said information at said auxiliary output is less advanced in said register than that corresponding to said respective output signal.
Claim 3
Dependent Claim 34 words
The circuit arrangement of claim 1, wherein a selector switch is connected to said second switching means so as to selectively connect the respective inputs of each register to either of its corresponding outputs.
Claim 4
Dependent Claim 30 words
The circuit arrangement of claim 1, wherein the speed at which the information is applied to said shift registers can be varied proportionally with write-in clock frequency of said registers.
Claim 5
Dependent Claim 26 words
The circuit arrangement of claim 1, wherein said auxiliary outputs are connected approximately four-tenths of the way along said registers from said inputs to said outputs.
Claim 6
Dependent Claim 241 words
A circuit arrangement for playing back recorded information in a tempo which differs from the original recording tempo, and particularly for playing back retarded or accelerated speech while maintaining the correct pitch, said circuit arrangement comprising: a first shift register; a second shift register; means for supplying information in a desired tempo to said registers; a first electronic switch disposed between said registers and said information supplying means to alternately apply said information to said registers; a second electronic switch operated in phase opposition to said first switch, said second electronic switch connected to said registers for alternatively deriving an output signal therefrom; means for supplying said registers with clock pulses for advancing information therethrough; first switching means disposed between said registers and said clock pulse supplying means, for alternately, but in phase opposition, applying said clock pulses to said registers, frequencies of said clock pulses jumping from one value to another at each change-over of said switching means, a ratio of these frequencies beiNg equal to a speed ratio between the speed at which said information is applied to the shift registers and the speed at which said information is recorded; and second switching means connected to respective registers, for connecting an output of a respective register to an input thereof, said second switching means being gradually operated, and simultaneously therewith, the first electronic switch being gradually changed over at an instant before said first switching means is changed over.
Claim 7
Dependent Claim 241 words
A circuit arrangement for playing back recorded information in a tempo which differs from the original recording tempo, and particularly for playing back retarded or accelerated speech while maintaining the correct pitch, said circuit arrangement comprising: a first shift register; a second shift register; means for supplying information in a desired tempo to said registers; a first electronic switch disposed between said registers and said information supplying means to alternately apply said information to said registers; a second electronic switch operated in phase opposition to said first switch, said second electronic switch connected to said registers for alternatively deriving an output signal therefrom; means for supplying said registers with clock pulses for advancing information therethrough; first switching means disposed between said registers and said clock pulse supplying means, for alternately, but in phase opposition, applying said clock pulses to said registers, frequencies of said clock pulses jumping from one value to another at each change-over of said switching means, a ratio of these frequencies beiNg equal to a speed ratio between the speed at which said information is applied to the shift registers and the speed at which said information is recorded; and second switching means connected to respective registers, for connecting an output of a respective register to an input thereof, said second switching means being gradually operated, and simultaneously therewith, the first electronic switch being gradually changed over at an instant before said first switching means is changed over.
Claim 8
Dependent Claim 35 words
The circuit arrangement of claim 5, wherein the second electronic switch is gradually changed over in a time interval in which said first switching means applies clock pulses of the same frequency to each register.
Claim 9
Dependent Claim 57 words
The circuit arrangement of claim 6, comprising in addition means for determining an equality instant when the information at the output of said first and second registers is equal and varying in the same sense, and means for controlling the change-over instant of at least the second electronic switch in response to determination of said equality instant.
Claim 10
Dependent Claim 38 words
The circuit arrangement of claim 7, wherein a lower one of said clock frequency signals opens a gate for passing a change-over instruction from at least the second electronic switch as soon as said time interval is reached.

References Cited (Backward Citations)

US3104284A Cited
US3293613A Cited
US3467783A Cited
US3499996A Cited
US3634625A Cited
US3621150A Cited
US3681756A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-12-16 1978-06-17 1978-12-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-12-16 1982-06-17 1982-12-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-12-16 1986-06-17 1986-12-17 $7700.00 Window Closed / Lapsed

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