Stabilized delay line oscillator

Claim 2

A stabilized pulse generating circuit comprising: a delay line clock constructed to provide a repetitive alternating waveform clock output in response to an input signal; and means coupled to said delay line clock for compensating for changes in the delay line timing period of the clock in order to stabilize the period of the clock output at a selected value.

Claim 3

The circuit of claim 1 wherein said means for compensating comprises means for comparing the output of said delay line clock against a fixed number N during a reference period (T r ) and providing a signal to control said clock period such that the output of the clock is stabilized at a frequency equal to (T r /N).

Claim 4

The circuit of claim 1 wherein said delay line clock comprises, a delay line having an input and output, gating means having a plurality of inputs and an output coupled to the input of said delay line for providing a pulse input to said delay line, the output of the delay line being coupled to one of the inputs to said gating means, and means for providing a gating pulse to one of the other inputs of the gating means to provide said input signal for initiating the repetitive alternating waveform clock output.

Claim 5

The circuit of claim 3 wherein said means for compensating comprises, means responsive to the output of said gating means for providing a variable width pulse to another of the inputs to said gating means, and means coupled to said means for providing a variable width pulse for controlling the width of said pulse.

Claim 6

The circuit of claim 3 wherein said gating means comprises a NAND-gate and wherein said means for compensating comprises, a one-shot multivibrator having an input coupled to the NAND-gate output and an output coupled to provide a variable width pulse to another one of the NAND-gate inputs, and a variable voltage source coupled to control the width of the pulse output of the one-shot multivibrator.

Claim 7

A stabilized pulse generating circuit comprising: a delay line clock constructed to provide a clock output frequency including, a delay line having an input and output, gating means having a plurality of inputs and an output coupled to the input of said delay line for providing a pulse input to said delay line, the output of the delay line being coupled to one of the inputs to said gating means, and means for providing a gating pulse to one of the other inputs of the gating means to initiate the clock output; and means coupled to said delay line clock for stabilizing the period of the clock output including, means responsive to the output of said gating means for providing a variable width pulse to another of the inputs to said gating means, and means coupled to said means for providing a variable width pulse for controlling the width of said pulse including, means for providing a series of pulses separated in time by a precise reference period, counter means coupled to the output of said gating means and responsive to a gating pulse for counting the output pulses from said gating means during said reference period to provide a count output, means for comparing the count output against a fixed number N and providing a difference output, accumulator means responsive to said reference period pulses for storing the difference output at the time a reference pulse is received, and converter means coupled to the accumulator means for changing the output of the accumulator to a signal for controlling the width of said variable width pulse.

Claim 8

A stabilized pulse generating circuit comprising: a delay line clock constructed to provide a clock output frequency including, a delay line having an input and output, gating means having a plurality of inputs and an output coupled to the input of said delay line for providing a pulse input to said delay line, the output of the delay line being coupled to one of the inputs to said gating means, and means for providing a gating pulse to one of the other inputs of the gating means to initiate the clock output; and means coupled to said delay line clock for stabilizing the period of the clock output including, means responsive to the output of said gating means for providing a variable width pulse to another of the inputs to said gating means, and means coupled to said means for providing a variable width pulse for controlling the width of said pulse including, means for providing a series of pulses separated in time by a precise reference period, counter means coupled to the output of said gating means and responsive to a gating pulse for counting the output pulses from said gating means during said reference period to provide a count output, means for comparing the count output against a fixed number N and providing a difference output, accumulator means responsive to said reference period pulses for storing the difference output at the time a reference pulse is received, and converter means coupled to the accumulator means for changing the output of the accumulator to a signal for controlling the width of said variable width pulse.

Claim 9

The circuit of claim 6 wherein said means for providing the reference period pulses comprises a source of radar PRF pulses having an independently stable PRF period.

Claim 10

The circuit of claim 6 wherein said accumulator means comprises, a summing circuit having a first and second input and an output, and a storage register having an input coupled to store the output of the summing circuit upon receipt of a first reference period pulse and provide this output as input to said converter means until receipt of the next succeeding reference period pulse, said summing circuit having its first input coupled to receive said difference output and its second input coupled to receive the output of said storage register.

Claim 11

The circuit of claim 6 wherein said means for providing reference period pulses comprises, a crystal oscillator, a divider coupled to said oscillator and responsive to a gating pulse for providing a reference period output pulse at a time equal to NT after receipt of the gating pulse where T is the delay time of the delay line.

Claim 12

The circuit of claim 9 wherein the means for counting and the divider are coupled to receive the same gating pulse to initiate counting and division.

Claim 13

The circuit of claim 9 wherein said counter means is a digital counter, said means for comparing is a subtractor coupled to subtract the number N from the count output, and said converter means is a digital to analog converter.

Claim 14

The circuit of claim 11 further including means for digitally modifying N to change the delay line clock output frequency.

Claim 15

The circuit of claim 11 wherein said means for providing a variable width pulse comprises a one-shot multivibrator having an input coupled to the output of the gating means and an output coupled to provide a variable width pulse to said another of the inputs to said gating means, said multivibrator having a control input coupled to the analog voltage output of said digital to analog converter for changing the width of the multivibrator output pulse in response to the analog voltage.

Claim 16

The circuit of claim 13 wherein said gating means comprises a NAND-gate.