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US4103182A
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Programmable transfer gate array
Assignee: HP Inc
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Filing: 1976-09-01
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Granted: 1978-07-25
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Expires: 1996-09-01
Abstract
Abstract A programmable transfer gate array generates control signals as functions of input variables in a digital logic circuit by using two-phase logic requiring no quiescent D.C. power consumption.
Inventors
- 👤 Havyn E. Bradley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 14:36
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716; H03K19/1772
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
287 words
Apparatus for generating a digital control signal as a function of a plurality of digital input signals having first and second logic states, the apparatus comprising: storage means for storing a signal applied thereto; a pre-driver connected to said storage means for selectively applying a first signal thereto; a line driver for selectively generating a second signal; first and second transfer lines each connected between said line driver and said storage means and responsive to a selected first and second set of digital input signals respectively, each for transferring the second signal to said storage means in response to all of the selected digital input signals having the first value and said line driver generating the second signal; input means having a first output coupled to said first transfer line for generating a digital input signal of the first set having a logic state representative of a signal applied thereto and having a second output coupled to said second transfer line for generating a digital input signal of the second set having a logic state representative of the complement of the signal applied thereto; means for generating third and fourth signals; a third transfer line connected for selectively applying the third signal to said input means in response to a selected subset of the first set of digital input signals attaining the first logic state; a fourth transfer line connected for selectively applying the fourth signal to said input means in response to a selected subset of the second set of digital input signals attaining the first logic state; and output means connected to said storage means for selectively detecting the value stored by said storage means and for generating a digital control signal in response thereto.
Claim 2
Dependent Claim
287 words
Apparatus for generating a digital control signal as a function of a plurality of digital input signals having first and second logic states, the apparatus comprising: storage means for storing a signal applied thereto; a pre-driver connected to said storage means for selectively applying a first signal thereto; a line driver for selectively generating a second signal; first and second transfer lines each connected between said line driver and said storage means and responsive to a selected first and second set of digital input signals respectively, each for transferring the second signal to said storage means in response to all of the selected digital input signals having the first value and said line driver generating the second signal; input means having a first output coupled to said first transfer line for generating a digital input signal of the first set having a logic state representative of a signal applied thereto and having a second output coupled to said second transfer line for generating a digital input signal of the second set having a logic state representative of the complement of the signal applied thereto; means for generating third and fourth signals; a third transfer line connected for selectively applying the third signal to said input means in response to a selected subset of the first set of digital input signals attaining the first logic state; a fourth transfer line connected for selectively applying the fourth signal to said input means in response to a selected subset of the second set of digital input signals attaining the first logic state; and output means connected to said storage means for selectively detecting the value stored by said storage means and for generating a digital control signal in response thereto.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-07-24 | 1982-01-23 | 1982-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-07-24 | 1986-01-23 | 1986-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-07-24 | 1990-01-23 | 1990-07-25 | $7700.00 | Window Closed / Lapsed |