Patent US4101967A successfully refreshed from Google Patents.
US4101967A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single bit logic microprocessor
Assignee: TENDY ELECTRONICS Co
•
Filing: 1976-05-19
•
Granted: 1978-07-18
•
Expires: 1996-05-19
Abstract
Abstract A single bit recycling microprocessor which performs sequential and combinational logic equations. The microprocessor has exclusive input and output instructions and performs three basic logic operations, two of which are performed concurrently on each data input. The processor substitutes read only memory (ROM) for a network of logic gates, multiplexers, decoders, flip-flops and counters. The simulation of J-K flip-flops is accomplished by a tandem operation of two R-S flip-flops.
Inventors
- 👤 Marian Stanislaw Hajduk
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 13:40
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/11; G06F17/12; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/05; G05B2219/00; G05B2219/10; G05B2219/13; G05B2219/13058
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
298 words
A logic microprocessor comprising in combination: a single serially fed input data controller means having a data input, a control input, and a single data output; first and second logic operator means each having a respective single data input commonly coupled to said single data output of said input data controller means and each being fed the same serial data thereby and a single data output; data selector means having a pair of data inputs respectively coupled to the single data output of said first and second logic operator means, a control input and a data output; an instruction word memory, means for accessing instruction words from said memory, and a decoder responsive to said instruction words for providing a control signal output comprised of at least first and second instruction bits, said first instruction bit being coupled to said first and second logic operator means for enabling said operator means, said second instruction bit being coupled to said input data controller means and said data selector means; said input data controller means including means responsive to said second instruction bit to selectively provide a data output signal having either a first (true) or second (not) logic value of the input data applied to said data input thereof; said first logic operator means including means set by one of said logic values to perform a predetermined first type of logic operation thereon, said second logic operator means including means set by one of said logic values to perform a predetermined second type of logic operation thereon, and said data selector means including means responsive to said second instruction bit to provide a data output signal at its data output selectively either the output of said first logic operator means or the output of said second logic operator means.
Claim 2
Dependent Claim
298 words
A logic microprocessor comprising in combination: a single serially fed input data controller means having a data input, a control input, and a single data output; first and second logic operator means each having a respective single data input commonly coupled to said single data output of said input data controller means and each being fed the same serial data thereby and a single data output; data selector means having a pair of data inputs respectively coupled to the single data output of said first and second logic operator means, a control input and a data output; an instruction word memory, means for accessing instruction words from said memory, and a decoder responsive to said instruction words for providing a control signal output comprised of at least first and second instruction bits, said first instruction bit being coupled to said first and second logic operator means for enabling said operator means, said second instruction bit being coupled to said input data controller means and said data selector means; said input data controller means including means responsive to said second instruction bit to selectively provide a data output signal having either a first (true) or second (not) logic value of the input data applied to said data input thereof; said first logic operator means including means set by one of said logic values to perform a predetermined first type of logic operation thereon, said second logic operator means including means set by one of said logic values to perform a predetermined second type of logic operation thereon, and said data selector means including means responsive to said second instruction bit to provide a data output signal at its data output selectively either the output of said first logic operator means or the output of said second logic operator means.
Claim 3
Dependent Claim
32 words
The apparatus as defined by claim 1 wherein said first logic operator means is set by said first logic value and said second logic operator is set by said second logic value.
Claim 4
Dependent Claim
131 words
The apparatus as defined by claim 1 and additionally including a random access memory utilized for storing intermediate results of predetermined logic operations of said first and second logic operator means and having a control input coupled to said decoder and being responsive to said first instruction bit therefrom to selectively fetch data from said data selector means or output stored data to said input data controller means and having a data input coupled to the data output of said data selector means and a data output coupled to the data input of said input data controller means, and wherein the enablement of said first and second logic operator means by said first instruction bit comprises being reset to an initial state to thereafter perform a predetermined type of logic operation.
Claim 5
Dependent Claim
99 words
The apparatus as defined by claim 3 and additionally including: another data selector means having a plurality of data inputs and a data output, said data output being coupled to said data input of said input data controller means, said plurality of data inputs being coupled to respective input means, output decoder means having a data input coupled to the data output of said data selector means and providing at least one data output; and an instruction decoder coupled to said another data selector means, said random access memory and said output decoder for applying instruction control signals thereto.
Claim 6
Dependent Claim
73 words
The apparatus as defined by claim 4 and additionally including output data controller means having a data input coupled to the data output of said data selector means and having a data output coupled to the input of said random access memory for storing the output of said output data controller means, said random access memory being operative to store said output in response to an instruction control signal from said instruction decoder.
Claim 7
Dependent Claim
53 words
The apparatus as defined by claim 5 wherein said output decoder means includes internal memory means for storing data output signals from said output data controller means in response to an instruction control signal and having a plurality of output lines adapted to provide a respective stored data value concurrently thereon in parallel.
Claim 8
Dependent Claim
45 words
The apparatus as defined by claim 4 and additionally including a read only memory, having a stored program, coupled to said instruction decoder for providing sequence control signals to said instruction decoder whereupon said decoder becomes operative to generate said first and second instruction bits.
Claim 9
Dependent Claim
17 words
The apparatus as defined by claim 7 wherein said read only memory comprises an electrically programmable memory.
Claim 10
Dependent Claim
52 words
The apparatus as defined by claim 7 and additionally including an address register and a clock generator, said clock generator being coupled to said address register for applying operation timing signals thereto, said address register being coupled to said read only memory for addressing the stored program in said read only memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-07-17 | 1982-01-16 | 1982-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-07-17 | 1986-01-16 | 1986-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-07-17 | 1990-01-16 | 1990-07-18 | $7700.00 | Window Closed / Lapsed |