Abstract A computer system which is especially suitable for small scale computers, and which includes a main memory, a scratch pad memory having storage locations for main memory addresses and for operands, a P register for containing the address of any storage location in the scratch pad memory currently used as a program counter, and an instruction register including a portion I for an operation code, and a portion N for the address of any storage location in said scratch pad memory. During an instruction fetch cycle, the contents of the P register are used to address the current program counter location in the scratch pad memory, the contents of the program counter location are used to address the main memory and transfer an instruction therefrom to the instruction register, and the contents of the program counter location are incremented. During an instruction execute cycle, the program can cause any other scratch pad storage location to become the current program counter by transferring the contents of the portion N of the instruction register to the P register.
A computer system, comprising a main memory, a scratch pad memory having storage locations for main memory addresses and for operands, a P register for containing the address of any storage location in said scratch pad memory currently used as a program counter, an instruction register including a portion I for an operation code, and a portion N for the address of any storage location in said scratch pad memory, means to perform an instruction fetch cycle including, means utilizing the contents of the P register to address the current program counter location in said scratch pad memory, means using the contents of the program counter location to address said main memory and transfer an instruction therefrom to said instruction register, and means to modify the contents of the program counter location, and means to perform an instruction execute cycle including means to decode the contents of the I portion of the instruction register to cause a transfer of the contents of the N portion of the instruction register to said P register, whEreby the storage location in said scratch pad memory utilized as a program counter can be changed to any desired location therein.
Claim 2
Dependent Claim
195 words
A computer system, comprising a main memory, a scratch pad memory having storage locations for main memory addresses and for operands, a P register for containing the address of any storage location in said scratch pad memory currently used as a program counter, an instruction register including a portion I for an operation code, and a portion N for the address of any storage location in said scratch pad memory, means to perform an instruction fetch cycle including, means utilizing the contents of the P register to address the current program counter location in said scratch pad memory, means using the contents of the program counter location to address said main memory and transfer an instruction therefrom to said instruction register, and means to modify the contents of the program counter location, and means to perform an instruction execute cycle including means to decode the contents of the I portion of the instruction register to cause a transfer of the contents of the N portion of the instruction register to said P register, whEreby the storage location in said scratch pad memory utilized as a program counter can be changed to any desired location therein.