Patent US4101921A successfully refreshed from Google Patents.
US4101921A
Expired / Lapsed
US
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Memory type insulating gate field effect semiconductor device
Assignee: Sony Corp
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Filing: 1977-02-25
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Granted: 1978-07-18
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Expires: 1997-02-25
Abstract
Abstract In a memory type insulated gate field effect semiconductor device including a semiconductor layer of one conductivity type, a source region of the opposite conductivity type formed in the surface of the semiconductor layer, a drain region of the opposite conductivity type formed in the surface of the semiconductor layer, a gate insulating layer affixed to the surface of the semiconductor layer, and a gate electrode deposited on the surface of the gate insulating layer, the gate insulating layer has a pair of thick gate guarding portions which exist on side of the source and drain regions, and a thin memory portion intermediate between the thick gate guarding portions, and a surface impurity concentration per square centimeter of the semiconductor layer under the thick gate guarding portions is different from a surface impurity concentration per square centimeter of the semiconductor layer under the tin memory portion. The voltage difference between the threshold voltages of the semiconductor device at the memorized state and at the non-memorized state can be increased, and the read-out voltage of the semiconductor device can be reduced. The circuit design is simplified.
Inventors
- 👤 Takashi Shimada
- 👤 Kenichi Inoue
- 👤 Takaji Ohtsu
- 👤 Hidenobu Mochizuki
- 👤 Jiro Yamaguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 05:47
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D30/00; H10D30/60; H10D30/69; H10P30/21; H10P30/212
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
194 words
In a memory type insulated gate field effect semiconductor device including a semiconductor layer of one conductivity type having one surface, a source region of the opposite conductivity type formed adjacent to said one surface of said semiconductor layer, a drain region of the opposite conductivity type formed adjacent to said one surface of said semiconductor layer, a gate insulating layer affixed to the surface of said semiconductor layer, comprising a first insulating layer having a pair of thick gate guarding portions adjacent said source and drain regions, and a thin memory portion intermediate between said thick gate guarding portions and second insulating layer covering, said thin memory portion being between said thick gate portions, and a gate electrode deposited on the surface of said gate insulating layer, the improvement comprising means for shifting a threshold voltage of said thin memory portion substantially closer to a threshold voltage of said thick guarding portions, said means including a doped region of P type conductivity adjacent to said one surface under said thin memory portion and having a different surface impurity concentration than a surface impurity concentration of said semiconductor layer under said thick guarding portions.
Claim 2
Dependent Claim
194 words
In a memory type insulated gate field effect semiconductor device including a semiconductor layer of one conductivity type having one surface, a source region of the opposite conductivity type formed adjacent to said one surface of said semiconductor layer, a drain region of the opposite conductivity type formed adjacent to said one surface of said semiconductor layer, a gate insulating layer affixed to the surface of said semiconductor layer, comprising a first insulating layer having a pair of thick gate guarding portions adjacent said source and drain regions, and a thin memory portion intermediate between said thick gate guarding portions and second insulating layer covering, said thin memory portion being between said thick gate portions, and a gate electrode deposited on the surface of said gate insulating layer, the improvement comprising means for shifting a threshold voltage of said thin memory portion substantially closer to a threshold voltage of said thick guarding portions, said means including a doped region of P type conductivity adjacent to said one surface under said thin memory portion and having a different surface impurity concentration than a surface impurity concentration of said semiconductor layer under said thick guarding portions.
Claim 3
Dependent Claim
83 words
A memory type insulated gate field effect semiconductor device according to claim 1, in which said surface impurity concentration of said doped region under said thin memory portion which is 4 × 10 11 to 1 × 10 12 /cm 2 , is lower than said surface impurity concentration of said semiconductor layer under said thick gate guarding portions, and the conductivity type of the surface region of said semiconductor layer under said thin memory portion is converted to the opposite conductivity type.
Claim 4
Dependent Claim
72 words
A memory type insulated gate field effect semiconductor device according to claim 1, in which said surface impurity concentration of said doped region under said thin memory portion which is 5 × 10 11 to 2 × 10 12 /cm 2 , is higher than said surface impurity concentration of said semiconductor layer under said thick gate guarding portions, and the doped region and semiconductor layer are of the same conductivity type.
Claim 5
Dependent Claim
32 words
A memory type insulating gate field effect semiconductor device according to claim 1, in which the thickness of said first insulating layer of said thin memory portion is 20 to 30 A.
Claim 6
Dependent Claim
33 words
A memory type insulating gate field effect semiconductor device according to claim 1, in which the thickness of said first insulating layer of said thick gate guarding portions is 500 to 1000 A.
Claim 7
Dependent Claim
22 words
A memory type insulating gate field effect semiconductor device according to claim 1, in which said first insulating layer is silicon dioxide.
Claim 8
Dependent Claim
22 words
A memory type insulating gate field effect semiconductor device according to claim 1, in which said second insulating layer is silicon nitride.
Claim 9
Dependent Claim
31 words
A memory type insulating gate field effect semiconductor device according to claim 1, in which both edges of said doped region are aligned with both edges of said thin memory portion.
Claim 10
Dependent Claim
44 words
A memory type insulating gate field effect semiconductor device according to claim 1 wherein said means for shifting shifts the threshold voltage of the thin memory portion so that it is substantially the same as the threshold voltage of the thick gate guarding portions.
References Cited (Backward Citations)
US3877055A
Cited
US4011576A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-07-17 | 1982-01-16 | 1982-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-07-17 | 1986-01-16 | 1986-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-07-17 | 1990-01-16 | 1990-07-18 | $7700.00 | Window Closed / Lapsed |