Patent US4099232A successfully refreshed from Google Patents.
US4099232A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interval timer arrangement in a microprocessor system
Assignee: Mos Technology Inc
•
Filing: 1976-09-14
•
Granted: 1978-07-04
•
Expires: 1996-09-14
Abstract
Abstract An interval timer in a MOS IC microprocessor system uses a countdown register of as many stages as the data bus lines (8) but effectively doubles the capacity of that register, without increasing the number of data bus lines or repetitive loading, by interposing a prescale divide-down register between the system clock and the countdown register. The prescale register divides the system clock by one of several selectable factors equal to non-contiguous powers of two (e.g., by 1, 8, 64 or 1,024) to establish respective prescale time periods (of 1, 8, 64 or 1024 system clocK pulses). One of the several possible prescaling factors is selected by a pair of lines from the system address bus. As a result, the interval timer can be configured with one load operation for an interval within a range which was possible in the prior art only with double the number of data lines and double the length of the countdown register. Chip layout is thus optimized, and the number of control lines needed to access timer functions is reduced, with acceptable loss of flexibility.
Inventors
- 👤 William D. Mensch, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:33
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F9/4825
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
138 words
An interval timer for a microprocessor system having a plurality of data bus lines, a plurality of address bus lines and a clock, said interval timer comprising: a prescale divide-down register receiving the clock and providing a selectable one of a plurality of outputs which are divisions of the clock by noncontiguous powers of two; means for applying a subset of the address bus lines to the prescale register to select one of said outputs thereof; a countdown register; means for loading the countdown register with a selected number through the data bus lines; means for applying the selected output of the prescale register to the countdown register to cause a countdown of said number loaded therein; an interrupt flag register; and means for loading the interrupt flag register when the countdown register reaches the count of zero.
Claim 2
Dependent Claim
138 words
An interval timer for a microprocessor system having a plurality of data bus lines, a plurality of address bus lines and a clock, said interval timer comprising: a prescale divide-down register receiving the clock and providing a selectable one of a plurality of outputs which are divisions of the clock by noncontiguous powers of two; means for applying a subset of the address bus lines to the prescale register to select one of said outputs thereof; a countdown register; means for loading the countdown register with a selected number through the data bus lines; means for applying the selected output of the prescale register to the countdown register to cause a countdown of said number loaded therein; an interrupt flag register; and means for loading the interrupt flag register when the countdown register reaches the count of zero.
Claim 3
Dependent Claim
145 words
An interval timer for a microprocessor system having a plurality of data bus lines, a plurality of address bus lines and a clock providing clock pulses at a uniform rate, said interval timer comprising: a prescale divide-down register receiving the clock pulses and providing a selectable one of a plurality of outputs which are pulses at rates which are divisions of the clock rate by noncontiguous powers to two; means for applying a subset of the address bus lines to the prescale register to select one of said outputs thereof; a counting register; means for applying the selected output of the prescale register to the counting register to cause the counting register to count the pulses provided at the selected output of the prescale register; an interrupt flag register; and means for loading the interrupt flag register when the counting register reaches a selected count.
Claim 4
Dependent Claim
145 words
An interval timer for a microprocessor system having a plurality of data bus lines, a plurality of address bus lines and a clock providing clock pulses at a uniform rate, said interval timer comprising: a prescale divide-down register receiving the clock pulses and providing a selectable one of a plurality of outputs which are pulses at rates which are divisions of the clock rate by noncontiguous powers to two; means for applying a subset of the address bus lines to the prescale register to select one of said outputs thereof; a counting register; means for applying the selected output of the prescale register to the counting register to cause the counting register to count the pulses provided at the selected output of the prescale register; an interrupt flag register; and means for loading the interrupt flag register when the counting register reaches a selected count.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-07-03 | 1982-01-02 | 1982-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-07-03 | 1986-01-02 | 1986-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-07-03 | 1990-01-02 | 1990-07-04 | $7700.00 | Window Closed / Lapsed |