Logarithmic digital to analog converter

Claim 1

A digital to analog converter for converting a received multibit position binary word to a voltage whose amplitude ranges between negative and positive maximum values according to an expansion curve, the expansion curve consisting of a plurality of continuous substantially linear segments with each segment having a plurality of equally divided intervals, and the multibit position binary word having a first field for indicating a desired polarity, a second field for indicating a segment of the curve and a third field for indicating an interval of a segment, said converter comprising: a converter input for receiving the binary words; a converter outpt having first and second terminals; a decoding logic means connected to said converter input for decoding binary words, said decoding logic means having a first decoder means for decoding the first field to produce polarity indicating signals on a first set of decoding logic means outputs, a second decoder means for decoding the second field to produce segment indicating signals on a second set of decoding logic means outputs, and a third decoder means for decoding the third field to produce interval indicating signals on a third set of decoding logic means outputs; a potential source means including a source of positive and negative voltages having amplitudes directly related to said maximum values, and means connected to said first set of decoding means output terminals for emitting on a first potential-source-means output terminal one of the positive and negative voltages, a source of a compensating voltage for emitting on a second potential-source-means output terminal a compensating voltage whose polarity is determined by the signals on said first set of decoding means output terminals and a source of a reference voltage connected to the first terminal of said converter output; a group of first switches, each of said first switches having a control input connected to one of the outputs of said second set of outputs, a voltage input connected to said first potential-source means output terminal, and an output terminal; a group of second switches, each of said second switches having a control input connected to one of the outputs of said third set of outputs, a signal input and an output connected to the second terminal of said converter output; and a resistor ladder network comprising a plurality of serially connected longitudinal resistors, a common bus connected to said second potential-source-means output terminal, a plurality of transverse resistors, each of said longitudinal resistors having the same resistance and each of said transverse resistors having the same resistance, each of said transverse resistors connecting one of the junctions of said longitudinal resistors to said common bus, means for connecting some of the junctions of said longitudinal resistors to an output terminal of one of said first switches, one of said transverse resistors comprising a dividing resistor having one end connected to said common bus, a plurality of serially connected equivalued chain resistors, means for connecting one end of said plurality to the other end of said dividing resistor, means for connecting the other end of said plurality to the associated longitudinal resistor, and means for connecting each of the junctions of the resistors comprising said one transverse resistor to the signal input of one of said second switches.