Digital-to-analog converter

Claim 2

In a digital-to-analog converter for converting digital signals comprising n+m+1 bits each to analog signals with a nonlinear characteristic consisting of 2m 1 linear segments, having 2n amplitude stages comprising a coder operating according to the iterative process through the use of a first decoder circuit element, a second decoder circuit element and a third decoder circuit element, the first decoder circuit elements converting n bits of the digital signal in a resistor-ladder network having resistors that are adequate for a binay staggering of values to an analog control signal for the second decoder circuit element, the resistor-ladder network of the first decoder circuit element including a further resistor which can be made operative in the event that at least one of the m bits of the digital signal is formed by a binary 1, the second decoder circuit element comprising a resistor-ladder network having resistors that are adequate for a binary staggering of values, said resistors being made operative according to the value of the m binary bits of the digital signal and by said control signal, and the third decoder circuit element fixing the polarity of an output signal to be transmitted from the second decoder circuit element to a decoder output according to the remaining one bit in the digital signal, the improvement comprising: a common resistance ladder network shared by said first and second decoder elements wherein all shunt and end resistances have substantially one and the same resistance value, all remaining resistances being of twice said one value, constant current source means connected to n adjacent junction points formed by one of said remaining resistances and at least one said shunt resistance each, said n junction points being energized in accordance with n binary one bits of said digital signal, a second junction point adjoining said n junction points and formed by one of said remaining resistances and two of said shunt resistances, said second junction point being connected to be energized by said constant current in the event that at least one of m bits of the data signal is a binary one, means for selectively connecting an output of said converter between one of said remaining resistances and at least one of said shunt resistances with one 2m-1 junction points adjoining said junction points, said one junction point being determined by the value of the m binary one bits of the digital signal.

Claim 3

The digital-to-analog converter as defined in claim 1, wherein the polarities of said constant currents are determined by the remaining one bit of the digital signal concerned.

Claim 4

The digital-to-analog converter as defined in claim 1, wherein there is inserted intermediate said converter output and said resistance ladder network a changeover stage which transmits the signal routed thereto with one or another polarity as a function of the value of the remaining one bit of the digital signal.

Claim 5

In a digital-to-analog converter for converting digital signal comprising n+m+1 bits each to analog signals with a non-linear characteristic comprising 2m 1 linear segments having 2n amplitude stages comprising a coder operating according to the iterative process through the use of a first decoder circuit element, a second decoder circuit element, and a third decoder circuit element, the first decoder circuit element converting the n bits of the digital signal in a resistor-ladder network, having resistors that are adequate for a binary staggering of values, to an analog control signal for the second decoder circuit element, the resistor-ladder network of the first decoder circuIt element including a further resistor which can be made operative in the event that at least one of the m bits of the signal if formed by a binary one, the second decoder circuit element comprising a resistor-ladder network having resistors that are adequate for a binary staggering of values, said resistors being made operative in accordance with the value of the m binary bits of the digital signal and affecting said control signal accordingly, and the third decoder circuit element fixing the polarity of an output signal to be transmitted from the second decoder circuit element to a decoder output according to the remaining one bit, the improvement comprising: common resistance ladder network means, shared by said first and second decoder elements, having shunt resistances and resistances disposed at both ends of said ladder network, each of said shunt and end resistances having substantially one and the same resistance value, all remaining resistances in said ladder network having twice said one value, one end of said ladder network being connected to an output of said converter, a group of n neighboring junction points being formed on said ladder network, each junction point being defined by one of said remaining resistances and at least one of said shunt resistances, one of said junction points of said group turned toward said one end of said ladder network has a distance from said one end corresponding to 1 to 2m 1 junction points in accordance with the value of the m binary one bits of said digital signal, constant current source means selectively connectable to ones of said group of junction points according to the n binary one bits of said digital signal, and means connecting said constant current source means to a junction between one of said remaining resistance means and a shunt resistance means adjoining said n neighboring junctions in the event that at least one of the m bits of said digital signal is a binary one.

Claim 6

In a digital-to-analog converter for converting digital signal comprising n+m+1 bits each to analog signals with a non-linear characteristic comprising 2m 1 linear segments having 2n amplitude stages comprising a coder operating according to the iterative process through the use of a first decoder circuit element, a second decoder circuit element, and a third decoder circuit element, the first decoder circuit element converting the n bits of the digital signal in a resistor-ladder network, having resistors that are adequate for a binary staggering of values, to an analog control signal for the second decoder circuit element, the resistor-ladder network of the first decoder circuIt element including a further resistor which can be made operative in the event that at least one of the m bits of the signal if formed by a binary one, the second decoder circuit element comprising a resistor-ladder network having resistors that are adequate for a binary staggering of values, said resistors being made operative in accordance with the value of the m binary bits of the digital signal and affecting said control signal accordingly, and the third decoder circuit element fixing the polarity of an output signal to be transmitted from the second decoder circuit element to a decoder output according to the remaining one bit, the improvement comprising: common resistance ladder network means, shared by said first and second decoder elements, having shunt resistances and resistances disposed at both ends of said ladder network, each of said shunt and end resistances having substantially one and the same resistance value, all remaining resistances in said ladder network having twice said one value, one end of said ladder network being connected to an output of said converter, a group of n neighboring junction points being formed on said ladder network, each junction point being defined by one of said remaining resistances and at least one of said shunt resistances, one of said junction points of said group turned toward said one end of said ladder network has a distance from said one end corresponding to 1 to 2m 1 junction points in accordance with the value of the m binary one bits of said digital signal, constant current source means selectively connectable to ones of said group of junction points according to the n binary one bits of said digital signal, and means connecting said constant current source means to a junction between one of said remaining resistance means and a shunt resistance means adjoining said n neighboring junctions in the event that at least one of the m bits of said digital signal is a binary one.

Claim 7

The digital-to-analog converter as defined in claim 4, wherein said constant current source means is connected to the junction points formed by one said remaining resistance and at least one shunt resistance each over a switch network containing a multiplicity of switches, which can each be triggered from an output of a control decoder having 2m outputs, to which the m bits of the digital signal concerned are routed.