Nonlinear decoder

Claim 1

A nonlinear decoder for converting binary signals into analog form where the binary signals include a total of n digits incorporating a smaller group of x digits, the most significant one of the n digits characterizing whether the analog signal is to be negative or positive, each of the (n-X-1) digits succeeding the first digit characterizing the level of a pedestal voltage, and the least significant and remaining x digits characterizing a supplementary voltage representing the difference between the encoded analog voltage and the pedestal voltage, said decoder comprising: a register recording the n digits of code to be decoded, two identical ladder networks formed of resistors, a first current generator responsive to signals representing one of the (n-x-1) digits following the first digit recorded in the register, said first current generator responding to said signals to supply current to the ladder network at a level to establish a pedestal voltage, additional current generators responsive to signals representing the last x digits and coupled to provide additional current to the ladder network to complete the reproduction of the analog signal, a zone decoder for providing control signals to establish zones characterized by a minimum voltage level, said zone decoder responding to the first digit to determine the polarity of succeeding digits and to direct said control signals to one of the two ladder networks accordingly, and gating means responsive to the control signals to control the application of said first current and said additional current to one of said ladder networks.