Random access-erasable read only memory cell

Claim 2

In a memory of the kind selectively operable in RAM and ROM modes, said memory comprising first and second inverters, each inverter having an output node cross-coupled to an input node of the other for forming a static RAM cell, the output node of each inverter of said RAM cell being selectively connected via the conduction paths of separate access transistors to respective digit lines, the control electrodes of said access transistors being connected to a common control line and each inverter including at least a first field effect transistor having an unbalanced impedance means associated therewith for providing ROM data retention, the improvement for providing RAM and EAROM operation of said memory, characterized in that: said unbalanced impedance means comprises a first variable-threshold transistor connected as a load in the drain circuit of said first field effect transistor in said first inverter and having a control electrode connected to the output of said second inverter; and a second variable threshold transistor connected as a load in the drain circuit of said first field effect transistor in said second inverter and having a control electrode connected to the output of the first inverter.

Claim 3

A memory as recited in claim 1 wherein: the source electrodes of said field effect transistors are connected to a point of reference potential; wherein the variable-threshold transistors comprise a pair of MNOS transistors connected at the drain electrodes thereof to respective drain electrodes of said field effect transistors and connected at the source electrodes thereof to an operating voltage node; and wherein means are provided for changing the voltage at said operating voltage node between a first value substantially equal to the potential at said point of reference potential and a second predetermined value in an EAROM read mode of operation.

Claim 4

A memory as recited in claim 2 further comprising: means for applying a potential greater than said predetermined value to a selected one of said output nodes and to said operating voltage node during a EAROM write operation.

Claim 5

A memory cell comprising, in combination: first and second digit lines; a terminal for an operating voltage; a first inverter comprising a conductor-insulator-semiconductor (CIS) transistor of a first conductivity type and a variable threshold transistor of a second conductivity type, each transistor having a conduction path and a control electrode, said control electrodes interconnected and said variable threshold transistor conduction path connected between said terminal and a first node and said CIS transistor conduction path connected between said first node and a point of reference potential; a second inverter comprising a second CIS transistor of said first conductivity type and a second variable threshold transistor of said second conductivity type, each transistor having a conduction path and a control electrode, said second CIS and said second variable threshold transistors control electrodes interconnected and connected in turn to said first node, said second variable threshold transistor conduction path connected between said terminal and a second node, said second CIS transistor connected between said second node and said point of reference potential and said second node connected to said first CIS transistor control electrode; first switch means for connecting said first digit line to said first node; second switch means for connecting said second digit line to said second node; and means for concurrently operating both switch means.

Claim 6

A memory cell comprising, in combination: first and second digit lines; a terminal for an operating voltage; a first inverter comprising a conductor-insulator-semiconductor (CIS) transistor of a first conductivity type and a variable threshold transistor of a second conductivity type, each transistor having a conduction path and a control electrode, said control electrodes interconnected and said variable threshold transistor conduction path connected between said terminal and a first node and said CIS transistor conduction path connected between said first node and a point of reference potential; a second inverter comprising a second CIS transistor of said first conductivity type and a second variable threshold transistor of said second conductivity type, each transistor having a conduction path and a control electrode, said second CIS and said second variable threshold transistors control electrodes interconnected and connected in turn to said first node, said second variable threshold transistor conduction path connected between said terminal and a second node, said second CIS transistor connected between said second node and said point of reference potential and said second node connected to said first CIS transistor control electrode; first switch means for connecting said first digit line to said first node; second switch means for connecting said second digit line to said second node; and means for concurrently operating both switch means.