Patent US4094012A successfully refreshed from Google Patents.
US4094012A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrically programmable MOS read-only memory with isolated decoders
Assignee: Intel Corp
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Filing: 1976-10-01
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Granted: 1978-06-06
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Expires: 1996-10-01
Abstract
Abstract A programmable and erasable MOS read-only memory employing floating gate memory cells. Unique, compact decoders allow the high voltage programming signal to be fully decoded without exposing the decoding transistors to the high voltage. The memory employs field-effect transistors having four different voltage thresholds. One such device is employed in the sense amplifiers to provide compensation for process variations and another device is used to allow the output buffers to be readily "powered-down".
Inventors
- 👤 George Perlegos
- 👤 Phillip J. Salsbury
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 13:57
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/08; G11C16/10; G11C16/12; G11C16/20
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
231 words
An electrically programmable MOS memory comprising: a plurality of memory cells, said cells requiring a first potential for reading and a second potential, higher than said first potential, for programming; input means; output means, coupled to said plurality of memory cells; decoding means comprising: a decoder for receiving a plurality of address signals from said input means and for providing said first potential when said address signals are in a predetermined state, said decoder coupled to said input means; voltage supply means for providing said second potential; coupling means comprising a field-effect transistor coupled between said decoder and said voltage supply means, said coupling means including means for applying a first signal to the gate of said transistor during reading and a second signal to the gate of said transistor during programming, said transistor for providing an electrical path during reading, and for providing an electrical path during programming if said address signals are in other than said predetermined state; said voltage supply means comprising a first and second depletion mode transistor coupled in series, said first transistor having its gate and one of its terminals coupled to said field-effect transistor of said coupling means and said second transistor having its gate and one of its terminals coupled to receive said second, higher potential; whereby said decoding means may be employed to select cells in said memory for reading and programming.
Claim 2
Dependent Claim
231 words
An electrically programmable MOS memory comprising: a plurality of memory cells, said cells requiring a first potential for reading and a second potential, higher than said first potential, for programming; input means; output means, coupled to said plurality of memory cells; decoding means comprising: a decoder for receiving a plurality of address signals from said input means and for providing said first potential when said address signals are in a predetermined state, said decoder coupled to said input means; voltage supply means for providing said second potential; coupling means comprising a field-effect transistor coupled between said decoder and said voltage supply means, said coupling means including means for applying a first signal to the gate of said transistor during reading and a second signal to the gate of said transistor during programming, said transistor for providing an electrical path during reading, and for providing an electrical path during programming if said address signals are in other than said predetermined state; said voltage supply means comprising a first and second depletion mode transistor coupled in series, said first transistor having its gate and one of its terminals coupled to said field-effect transistor of said coupling means and said second transistor having its gate and one of its terminals coupled to receive said second, higher potential; whereby said decoding means may be employed to select cells in said memory for reading and programming.
Claim 3
Dependent Claim
15 words
The MOS memory defined by claim 1 wherein said transistor comprises a depletion mode transistor.
Claim 4
Dependent Claim
24 words
The MOS memory defined by claim 2 wherein said second signal coupled to said gate of said depletion mode transistor is a ground signal.
Claim 5
Dependent Claim
28 words
The MOS memory defined by claim 3 including means for decoupling said decoder and said transistor from ground to conserve power, when said memory is not in use.
Claim 6
Dependent Claim
33 words
The MOS memory defined by claim 1 including logic means for coupling said decoder and one terminal of said transistor to ground when said address signals are in other than said predetermined states.
Claim 7
Dependent Claim
22 words
The MOS memory defined by claim 5 wherein said logic means is coupled to receive a single one of said address signals.
Claim 8
Dependent Claim
41 words
The MOS memory defined by claim 6 including a second one of said voltage supply means, coupling means and logic means and wherein said second logic means is coupled to receive the complement of said single one of said address signals.
Claim 9
Dependent Claim
276 words
An electrically programmable MOS memory comprising: a plurality of memory cells, said cells requiring a first potential for reading and a second potential, higher than said first potential, for programming; input means; output means, coupled to said plurality of memory cells; decoder means comprising: a first and second line; logic means coupled to said first and second lines, said logic means receiving a first address signal and its complement from said input means so as to ground one of said first and second lines; a decoder including a plurality of first transistors coupled in parallel between said first and second lines, said first transistors for receiving a plurality of second address signals from said input means, said decoder for providing said first potential on one of said first and second lines when said first and second address signals are in a predetermined state; a pair of voltage supply means for providing said second potential; coupling means comprising a pair of field-effect transistors, one of said field-effect transistors coupled between said first line and one of said voltage supply means, the other of said field-effect transistors coupled between said second line and the other of said voltage supply means, said coupling means including means for applying a first signal to the gates of said field-effect transistors during reading and a second signal to the gates of said field-effect transistors during programming, said field-effect transistors for providing an electrical path during reading, and for providing an electrical path during programming if said address signals are in other than said predetermined state; whereby said decoding means may be employed to select cells in said memory for reading and programming.
Claim 10
Dependent Claim
276 words
An electrically programmable MOS memory comprising: a plurality of memory cells, said cells requiring a first potential for reading and a second potential, higher than said first potential, for programming; input means; output means, coupled to said plurality of memory cells; decoder means comprising: a first and second line; logic means coupled to said first and second lines, said logic means receiving a first address signal and its complement from said input means so as to ground one of said first and second lines; a decoder including a plurality of first transistors coupled in parallel between said first and second lines, said first transistors for receiving a plurality of second address signals from said input means, said decoder for providing said first potential on one of said first and second lines when said first and second address signals are in a predetermined state; a pair of voltage supply means for providing said second potential; coupling means comprising a pair of field-effect transistors, one of said field-effect transistors coupled between said first line and one of said voltage supply means, the other of said field-effect transistors coupled between said second line and the other of said voltage supply means, said coupling means including means for applying a first signal to the gates of said field-effect transistors during reading and a second signal to the gates of said field-effect transistors during programming, said field-effect transistors for providing an electrical path during reading, and for providing an electrical path during programming if said address signals are in other than said predetermined state; whereby said decoding means may be employed to select cells in said memory for reading and programming.
Claim 11
Dependent Claim
14 words
The memory defined by claim 8 wherein said field-effect transistors are depletion mode transistors.
Claim 12
Dependent Claim
23 words
The memory defined by claim 9 wherein said second signal coupled to said gates of said depletion mode transistors is a ground signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-06-05 | 1981-12-05 | 1982-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-06-05 | 1985-12-05 | 1986-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-06-05 | 1989-12-05 | 1990-06-06 | $7700.00 | Window Closed / Lapsed |