High voltage integrated driver circuit

Claim 2

An integrated read mostly digital electronic memory array for storing information, comprising: a plurality of memory elements requiring significantly higher potentials for writing information than for reading information formed on a semiconductor substrate, a bit line also formed on said same semiconductor substrate and electrically connected to at least several of said memory elements; a high voltage integrated driver circuit also formed on said same semiconductor substrate connected to said bit line, said high voltage integrated driver circuit being connectable to two independent sets of a plurality of potential terminals, each said plurality of potential terminals being either a steady state potential level or a pulsating potential level, said high voltage integrated driver circuit comprising field effect transistors having predetermined avalanche breakdown potential, several of said potential terminals providing potential levels in excess of said predetermined avalanche breakdown, each said plurality of field effect transistors exposed to said higher than avalanche breakdown potential having a current path from its gating electrode to a suitable potential, thereby preventing the accumulation of avalanche breakdown charge.

Claim 3

A read mostly digital electronic memory array as in claim 1 wherein said plurality of memory elements are arranged in rows and columns, said bit line electrically connected to at least several of said memory elements arranged in a column, said memory array also comprising: a word line connected to at least several of said memory elements arranged in a row; and a word line driver circuit connected to said word line, said word line driver circuit being connectable to two independent sets of a plurality of potential terminals.

Claim 4

A read mostly digital electronic memory array as in claim 2 wherein each said plurality of potential terminals being either a steady state potential level or a pulsating potential level.

Claim 5

A read mostly memory array as in claim 3 wherein said word line driver circuit comprises field effect transistors having predetermined avalanche breakdown potentials.

Claim 6

A read mostly digital electronic memory array for storing information as in claim 1 wherein said bit line is also a sense line, said memory array further comprising: a sense amplifier circuit connected to said bit line.

Claim 7

A read mostly digital electronic memory array as in claim 5 wherein said sense amplifier is also connected to said high voltage integrated driver circuit and comprises: a pair of gateable means one connected to said bit line, the other connected to said high voltage integrated driver circuit, said gateable means being in their high impedance state during a write cycle when it is desired to write information into the memory cell and in their low impedance state during at least a portion of the read cycle when it is desired to read information from the memory element.

Claim 8

A read mostly digital electronic memory array for storing information, comprising: a plurality of memory elements arranged in rows and columns and requiring significantly higher potentials for writing information than for reading information; a plurality of bit lines each electrically connected to a column of said memory elements; a plurality of word lines each electrically connected to a row of said memory elements; a word line driver circuit connected to each of said plurality of word lines for driving a selected one of said plurality of rows of memory elements; a plurality of bit line driver circuits each connected to a column of said memory elements, said bit line driver circuit being a high voltage integrated driver circuit comprising a transistor having a control electrode, first and second controlled electrodes, and an impedance between said controlled electrodes being variable in response to one of several potential levels applied to the control electrode; means for selectively interconnecting said control electrode to one of said several potential levels thereby adjusting the impedance of said transistor to a predetermined level; means for interconnecting said first controlled electrode to an output; and means for selectively interconnecting said second controlled electrode either to a steady state potential level or to a pulse source having one of two potential levels.

Claim 9

A read mostly digital electronic memory array for storing information, comprising: a plurality of memory elements arranged in rows and columns and requiring significantly higher potentials for writing information than for reading information; a plurality of bit lines each electrically connected to a column of said memory elements; a plurality of word lines each electrically connected to a row of said memory elements; a word line driver circuit connected to each of said plurality of word lines for driving a selected one of said plurality of rows of memory elements; a plurality of bit line driver circuits each connected to a column of said memory elements, said bit line driver circuit being a high voltage integrated driver circuit comprising a transistor having a control electrode, first and second controlled electrodes, and an impedance between said controlled electrodes being variable in response to one of several potential levels applied to the control electrode; means for selectively interconnecting said control electrode to one of said several potential levels thereby adjusting the impedance of said transistor to a predetermined level; means for interconnecting said first controlled electrode to an output; and means for selectively interconnecting said second controlled electrode either to a steady state potential level or to a pulse source having one of two potential levels.

Claim 10

A read mostly digital electronic memory array for storing information, comprising: a plurality of memory elements requiring significantly higher potentials for writing information than for reading information; a bit line electrically connected to at least several of said memory elements; a high voltage integrated driver circuit connected to said bit line, said high voltage integrated driver circuit being connectable to two independent sets of a plurality of potential terminals; each said plurAlity of potential terminals being either a steady state potential level or a pulsating potential level, said high voltage integrated driver circuit comprising field effect transistors having predetermined avalanche breakdown potentials, several of said potential terminals providing potential levels in excess of said predetermined avalanche breakdown potential, each said plurality of field effect transistors exposed to said higher than avalanche breakdown potential having a current path from its gating electrode to ground potential, thereby preventing the accumulation of avalanche breakdown charge; said driver circuit comprising a transistor having a controlled electrode, first and second controlled electrodes, and an impedance between said controlled electrodes being variable in response to one of several potential levels applied to the control electrode; means for selectively interconnecting said control electrode to one of said several potential levels thereby adjusting the impedance of said transistor to a predetermined level; means for interconnecting said first controlled electrode to said bit line; and means for selectively interconnecting said second controlled electrode either to a steady state potential level or to a pulse source having one of two potential levels.

Claim 11

A read mostly digital electronic memory array for storing information, comprising: a plurality of memory elements requiring significantly higher potentials for writing information than for reading information; a bit line electrically connected to at least several of said memory elements; a high voltage integrated driver circuit connected to said bit line, said high voltage integrated driver circuit being connectable to two independent sets of a plurality of potential terminals; each said plurAlity of potential terminals being either a steady state potential level or a pulsating potential level, said high voltage integrated driver circuit comprising field effect transistors having predetermined avalanche breakdown potentials, several of said potential terminals providing potential levels in excess of said predetermined avalanche breakdown potential, each said plurality of field effect transistors exposed to said higher than avalanche breakdown potential having a current path from its gating electrode to ground potential, thereby preventing the accumulation of avalanche breakdown charge; said driver circuit comprising a transistor having a controlled electrode, first and second controlled electrodes, and an impedance between said controlled electrodes being variable in response to one of several potential levels applied to the control electrode; means for selectively interconnecting said control electrode to one of said several potential levels thereby adjusting the impedance of said transistor to a predetermined level; means for interconnecting said first controlled electrode to said bit line; and means for selectively interconnecting said second controlled electrode either to a steady state potential level or to a pulse source having one of two potential levels.

Claim 12

A read mostly memory array as in claim 8 wherein: said means for selectively interconnecting said second controlled electrode is connected to a pulse source having one of two potential levels, the difference between the potential levels of said two potential levels being in excess of the avalanche breakdown potential of said transistor, the gating electrode of said transistor being connected to the one of said two potential levels for adjusting the impedance of said transistor to its nonconductive state and providing a discharge path for preventing the accumulation of avalanche breakdown electrons.

Claim 13

A read mostly memory as in claim 8 wherein: said means for selectively interconnecting said second controlled electrode is connected to a steady state potential level, said potential level being less than the avalanche breakdown potential of said transistor; and means selectively interconnecting said control electrode and the controlled electrode connected to said bit line for maintaining said transistor off when the one of said several potential levels applied to the control electrode adjusts the impedance of said transistor to an off level. (thereby eliminating the effect of said transistor on the bit line during a read operation)

Claim 14

A read mostly digital electronic memory array for storing information, comprising: a plurality of memory elements requiring significantly higher potentials for writing information than for reading information; a bit line electrically connected to at least several of said memory elements; a high voltage integrated driver circuit connected to said bit line, said high voltage integrated driver circuit being connectable to two independent sets of a plurality of potential terminals; said bit line also being a sense line, said memory array further including a sense amplifier circuit connected to said bit line, said sense amplifier being also connected to said high voltage integrated driver circuit and comprising a pair of gateable means one connected to said bit line, the other connected to said high voltage integrated driver circuit, said gateable means being in their high impedance state during a write cycle when it is desired to write information into the memory cell and in their low impedance state during at least a portion of the read cycle when it is desired to read information from the memory element.

Claim 15

A read mostly digital electronic memory array for storing information, comprising: a plurality of memory elements requiring significantly higher potentials for writing information than for reading information; a bit line electrically connected to at least several of said memory elements; a high voltage integrated driver circuit connected to said bit line, said high voltage integrated driver circuit being connectable to two independent sets of a plurality of potential terminals; said bit line also being a sense line, said memory array further including a sense amplifier circuit connected to said bit line, said sense amplifier being also connected to said high voltage integrated driver circuit and comprising a pair of gateable means one connected to said bit line, the other connected to said high voltage integrated driver circuit, said gateable means being in their high impedance state during a write cycle when it is desired to write information into the memory cell and in their low impedance state during at least a portion of the read cycle when it is desired to read information from the memory element.